Module Definition
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Module : prim_packer_fifo
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.33 100.00 93.33 100.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_edn_req.u_prim_packer_fifo 74.14 100.00 96.55 100.00 0.00



Module Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.14 100.00 96.55 100.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.14 100.00 96.55 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 100.00 92.31 100.00 100.00 u_prim_edn_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_packer_fifo
Line No.TotalCoveredPercent
TOTAL1717100.00
ALWAYS8277100.00
CONT_ASSIGN9400
CONT_ASSIGN9611100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 unreachable
96 1 1
101 1 1
102 1 1
103 1 1
104 1 1
106 1 1
110 1 1
115 1 1
116 1 1
117 1 1


Cond Coverage for Module : prim_packer_fifo
TotalCoveredPercent
Conditions302893.33
Logical302893.33
Non-Logical00
Event00

 LINE       102
 EXPRESSION ((rready_i && rvalid_o) || clr_q)
             -----------1----------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T4,T5

 LINE       102
 SUB-EXPRESSION (rready_i && rvalid_o)
                 ----1---    ----2---
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T4,T5

 LINE       103
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       104
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       106
 EXPRESSION (clear_status ? '0 : (load_data ? ((depth_q + DepthOne)) : depth_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       106
 SUB-EXPRESSION (load_data ? ((depth_q + DepthOne)) : depth_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       110
 EXPRESSION (clear_data ? '0 : (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 SUB-EXPRESSION (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       115
 EXPRESSION (( ! (depth_q == FullDepth) ) && ((!clr_q)))
             --------------1-------------    -----2----
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       115
 SUB-EXPRESSION ( ! (depth_q == FullDepth) )
                    -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       115
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       117
 EXPRESSION ((depth_q == FullDepth) && ((!clr_q)))
             -----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       117
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

Branch Coverage for Module : prim_packer_fifo
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 106 3 3 100.00
TERNARY 110 3 3 100.00
IF 82 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 106 (clear_status) ? -2-: 106 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (clear_data) ? -2-: 110 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_packer_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 464535028 0 0 1143
ValidOPairedWithReadyI_A 464535028 0 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 464535028 0 0 1143

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 464535028 0 0 0

Line Coverage for Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo
Line No.TotalCoveredPercent
TOTAL1717100.00
ALWAYS8277100.00
CONT_ASSIGN9400
CONT_ASSIGN9611100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 unreachable
96 1 1
101 1 1
102 1 1
103 1 1
104 1 1
106 1 1
110 1 1
115 1 1
116 1 1
117 1 1


Cond Coverage for Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo
TotalCoveredPercent
Conditions292896.55
Logical292896.55
Non-Logical00
Event00

 LINE       102
 EXPRESSION ((rready_i && rvalid_o) || clr_q)
             -----------1----------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T4,T5

 LINE       102
 SUB-EXPRESSION (rready_i && rvalid_o)
                 ----1---    ----2---
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T4,T5

 LINE       103
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       104
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       106
 EXPRESSION (clear_status ? '0 : (load_data ? ((depth_q + DepthOne)) : depth_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       106
 SUB-EXPRESSION (load_data ? ((depth_q + DepthOne)) : depth_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       110
 EXPRESSION (clear_data ? '0 : (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 SUB-EXPRESSION (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       115
 EXPRESSION (( ! (depth_q == FullDepth) ) && ((!clr_q)))
             --------------1-------------    -----2----
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       115
 SUB-EXPRESSION ( ! (depth_q == FullDepth) )
                    -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       115
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       117
 EXPRESSION ((depth_q == FullDepth) && ((!clr_q)))
             -----------1----------    -----2----
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T4,T5

 LINE       117
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

Branch Coverage for Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 106 3 3 100.00
TERNARY 110 3 3 100.00
IF 82 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 106 (clear_status) ? -2-: 106 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (clear_data) ? -2-: 110 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 464535028 0 0 1143
ValidOPairedWithReadyI_A 464535028 0 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 464535028 0 0 1143

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 464535028 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%