Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	467392391	8010610	0	0
check_regwen_rd_A	467392391	2964	0	0
check_timeout_rd_A	467392391	2267	0	0
check_trigger_regwen_rd_A	467392391	2816	0	0
consistency_check_period_rd_A	467392391	2867	0	0
creator_sw_cfg_read_lock_rd_A	467392391	2367	0	0
direct_access_address_rd_A	467392391	1613	0	0
direct_access_wdata_0_rd_A	467392391	839	0	0
direct_access_wdata_1_rd_A	467392391	1047	0	0
integrity_check_period_rd_A	467392391	3087	0	0
intr_enable_rd_A	467392391	3468	0	0
owner_sw_cfg_read_lock_rd_A	467392391	2180	0	0
rot_creator_auth_codesign_read_lock_rd_A	467392391	2275	0	0
rot_creator_auth_state_read_lock_rd_A	467392391	1978	0	0
vendor_test_read_lock_rd_A	467392391	2260	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	8010610	0	0
T6	571974	112396	0	0
T7	0	52347	0	0
T14	0	58445	0	0
T17	0	116911	0	0
T18	0	76530	0	0
T19	0	114785	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T194	0	241089	0	0
T220	0	49217	0	0
T242	0	46640	0	0
T259	0	180362	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	2964	0	0
T6	571974	123	0	0
T14	0	93	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T238	0	115	0	0
T291	0	129	0	0
T295	0	81	0	0
T296	0	34	0	0
T297	0	120	0	0
T298	0	51	0	0
T299	0	93	0	0
T300	0	58	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	2267	0	0
T6	571974	158	0	0
T14	0	78	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T238	0	196	0	0
T291	0	140	0	0
T295	0	86	0	0
T296	0	49	0	0
T297	0	87	0	0
T298	0	59	0	0
T299	0	74	0	0
T300	0	70	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	2816	0	0
T6	571974	76	0	0
T14	0	94	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T238	0	124	0	0
T291	0	157	0	0
T295	0	110	0	0
T296	0	72	0	0
T297	0	81	0	0
T298	0	48	0	0
T299	0	78	0	0
T300	0	39	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	2867	0	0
T6	571974	120	0	0
T14	0	127	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T238	0	122	0	0
T291	0	135	0	0
T295	0	72	0	0
T296	0	92	0	0
T297	0	99	0	0
T298	0	60	0	0
T299	0	44	0	0
T300	0	82	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	2367	0	0
T6	571974	113	0	0
T14	0	85	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T238	0	150	0	0
T291	0	158	0	0
T295	0	94	0	0
T296	0	40	0	0
T297	0	95	0	0
T298	0	91	0	0
T299	0	68	0	0
T300	0	61	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	1613	0	0
T6	571974	187	0	0
T14	0	121	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T238	0	135	0	0
T291	0	193	0	0
T295	0	86	0	0
T296	0	26	0	0
T297	0	95	0	0
T298	0	59	0	0
T299	0	107	0	0
T300	0	71	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	839	0	0
T6	571974	63	0	0
T14	0	75	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T238	0	65	0	0
T291	0	83	0	0
T295	0	32	0	0
T296	0	3	0	0
T297	0	56	0	0
T298	0	35	0	0
T299	0	51	0	0
T300	0	37	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	1047	0	0
T6	571974	170	0	0
T14	0	61	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T238	0	99	0	0
T291	0	120	0	0
T295	0	58	0	0
T296	0	26	0	0
T297	0	61	0	0
T298	0	30	0	0
T299	0	43	0	0
T300	0	52	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	3087	0	0
T6	571974	119	0	0
T14	0	86	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T238	0	153	0	0
T291	0	132	0	0
T295	0	93	0	0
T296	0	40	0	0
T297	0	102	0	0
T298	0	82	0	0
T299	0	77	0	0
T300	0	60	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	3468	0	0
T6	571974	129	0	0
T8	0	30	0	0
T14	0	133	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T197	0	19	0	0
T234	0	53	0	0
T238	0	139	0	0
T244	0	22	0	0
T295	0	104	0	0
T296	0	37	0	0
T301	0	8	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	2180	0	0
T6	571974	134	0	0
T14	0	76	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T238	0	143	0	0
T291	0	130	0	0
T295	0	86	0	0
T296	0	16	0	0
T297	0	102	0	0
T298	0	107	0	0
T299	0	59	0	0
T300	0	78	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	2275	0	0
T6	571974	128	0	0
T14	0	109	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T238	0	103	0	0
T291	0	177	0	0
T295	0	94	0	0
T296	0	74	0	0
T297	0	84	0	0
T298	0	82	0	0
T299	0	88	0	0
T300	0	84	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	1978	0	0
T6	571974	121	0	0
T14	0	84	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T238	0	124	0	0
T291	0	119	0	0
T295	0	92	0	0
T296	0	24	0	0
T297	0	103	0	0
T298	0	48	0	0
T299	0	51	0	0
T300	0	89	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467392391	2260	0	0
T6	571974	144	0	0
T14	0	107	0	0
T36	196896	0	0	0
T64	14262	0	0	0
T77	10123	0	0	0
T104	23222	0	0	0
T105	39901	0	0	0
T106	12633	0	0	0
T138	16121	0	0	0
T173	8101	0	0	0
T174	42571	0	0	0
T238	0	162	0	0
T291	0	166	0	0
T295	0	71	0	0
T296	0	32	0	0
T297	0	101	0	0
T298	0	40	0	0
T299	0	79	0	0
T300	0	86	0	0