Module Definition
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Module Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.17 94.16 96.15 96.92 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_tx[1].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.17 94.16 96.15 96.92 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_tx[2].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.17 94.16 96.15 96.92 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_tx[3].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.17 94.16 96.15 96.92 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_tx[4].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.17 94.16 96.15 96.92 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T3,T104,T173 Yes T3,T104,T173 INPUT
alert_req_i Yes Yes T2,T10,T5 Yes T2,T10,T5 INPUT
alert_ack_o Yes Yes T2,T10,T5 Yes T2,T10,T5 OUTPUT
alert_state_o Yes Yes T2,T10,T5 Yes T2,T10,T5 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T2,T3,T10 Yes T2,T3,T10 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T2,T3,T10 Yes T2,T3,T10 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T3,T104,T173 Yes T3,T104,T173 INPUT
alert_req_i Yes Yes T10,T13,T110 Yes T10,T13,T110 INPUT
alert_ack_o Yes Yes T10,T13,T110 Yes T10,T13,T110 OUTPUT
alert_state_o Yes Yes T10,T13,T110 Yes T10,T13,T110 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T3,T10,T13 Yes T3,T10,T13 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T3,T10,T13 Yes T3,T10,T13 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[1].u_prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T3,T104,T173 Yes T3,T104,T173 INPUT
alert_req_i Yes Yes T2,T10,T5 Yes T2,T10,T5 INPUT
alert_ack_o Yes Yes T2,T10,T5 Yes T2,T10,T5 OUTPUT
alert_state_o Yes Yes T2,T10,T5 Yes T2,T10,T5 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T2,T3,T10 Yes T2,T3,T10 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T2,T3,T10 Yes T2,T3,T10 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[2].u_prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T3,T104,T173 Yes T3,T104,T173 INPUT
alert_req_i Yes Yes T22,T23,T24 Yes T22,T23,T24 INPUT
alert_ack_o Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
alert_state_o Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T3,T104,T173 Yes T3,T104,T173 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T3,T104,T173 Yes T3,T104,T173 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[3].u_prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T3,T104,T173 Yes T3,T104,T173 INPUT
alert_req_i Yes Yes T22,T23,T24 Yes T22,T23,T24 INPUT
alert_ack_o Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
alert_state_o Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T3,T104,T173 Yes T3,T104,T173 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T3,T104,T173 Yes T3,T104,T173 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[4].u_prim_alert_sender
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 14 14 100.00
Total Bits 0->1 7 7 100.00
Total Bits 1->0 7 7 100.00

Ports 7 7 100.00
Port Bits 14 14 100.00
Port Bits 0->1 7 7 100.00
Port Bits 1->0 7 7 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T3,T104,T173 Yes T3,T104,T173 INPUT
alert_req_i Unreachable Unreachable Unreachable INPUT
alert_ack_o Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
alert_state_o Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T3,T104,T173 Yes T3,T104,T173 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T3,T104,T173 Yes T3,T104,T173 OUTPUT

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