Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

26677222

1

T1

333

T2

2529

T3

1091

full_word

8651160

1

T1

161

T2

1516

T3

187

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35328072	1			T1	494		T2	4045		T3	1278
auto[TlIntgErrCmd]	98	1			T269	2		T270	10		T271	6
auto[TlIntgErrData]	93	1			T269	2		T270	4		T271	2
auto[TlIntgErrBoth]	119	1			T269	6		T270	6		T271	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9718816

1

T1

295

T2

3591

T3

1058

auto[1]

25609566

1

T1

199

T2

454

T3

220

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6112594	1			T1	220		T2	2255		T3	956
auto[TlIntgErrNone]	partial	auto[1]	20564349	1			T1	113		T2	274		T3	135
auto[TlIntgErrNone]	full_word	auto[0]	3606098	1			T1	75		T2	1336		T3	102
auto[TlIntgErrNone]	full_word	auto[1]	5045031	1			T1	86		T2	180		T3	85
auto[TlIntgErrCmd]	partial	auto[0]	26	1			T270	5		T271	2		T344	1
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T269	2		T270	4		T271	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T349	1		T275	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T270	1		T271	1		T344	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T269	1		T345	2		T343	4
auto[TlIntgErrData]	partial	auto[1]	46	1			T269	1		T270	4		T271	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T271	1		T348	1		T275	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T345	1		T350	1		T351	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T269	2		T270	1		T271	6
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T269	4		T270	5		T271	4
auto[TlIntgErrBoth]	full_word	auto[0]	10	1			T271	1		T345	1		T352	2
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T271	1		T343	1		T346	1