Unified Coverage Report :: Module :: prim_lfsr

Module : prim_lfsr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.95			87.95

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr	87.95			87.95
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr	87.95			87.95

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.95			87.95

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.95			87.95

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_double_lfsr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.95			87.95

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.95			87.95

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_double_lfsr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	146	87.95
Total Bits 0->1	83	73	87.95
Total Bits 1->0	83	73	87.95

Ports	5	4	80.00
Port Bits	166	146	87.95
Port Bits 0->1	83	73	87.95
Port Bits 1->0	83	73	87.95

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[15:0]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[16]	No	No		No		INPUT
entropy_i[21:17]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[24:22]	No	No		No		INPUT
entropy_i[27:25]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[28]	No	No		No		INPUT
entropy_i[29]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[30]	No	No		No		INPUT
entropy_i[32:31]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[34:33]	No	No		No		INPUT
entropy_i[36:35]	Yes	Yes	T119,*T133	Yes	T119,T133	INPUT
entropy_i[37]	No	No		No		INPUT
entropy_i[38]	Yes	Yes	*T119	Yes	T119	INPUT
entropy_i[39]	No	No		No		INPUT
state_o[39:0]	Yes	Yes	T10,T4,T5	Yes	T9,T10,T4	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	146	87.95
Total Bits 0->1	83	73	87.95
Total Bits 1->0	83	73	87.95

Ports	5	4	80.00
Port Bits	166	146	87.95
Port Bits 0->1	83	73	87.95
Port Bits 1->0	83	73	87.95

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[15:0]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[16]	No	No		No		INPUT
entropy_i[21:17]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[24:22]	No	No		No		INPUT
entropy_i[27:25]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[28]	No	No		No		INPUT
entropy_i[29]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[30]	No	No		No		INPUT
entropy_i[32:31]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[34:33]	No	No		No		INPUT
entropy_i[36:35]	Yes	Yes	T119,*T133	Yes	T119,T133	INPUT
entropy_i[37]	No	No		No		INPUT
entropy_i[38]	Yes	Yes	*T119	Yes	T119	INPUT
entropy_i[39]	No	No		No		INPUT
state_o[39:0]	Yes	Yes	T10,T4,T5	Yes	T9,T10,T4	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	146	87.95
Total Bits 0->1	83	73	87.95
Total Bits 1->0	83	73	87.95

Ports	5	4	80.00
Port Bits	166	146	87.95
Port Bits 0->1	83	73	87.95
Port Bits 1->0	83	73	87.95

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[15:0]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[16]	No	No		No		INPUT
entropy_i[21:17]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[24:22]	No	No		No		INPUT
entropy_i[27:25]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[28]	No	No		No		INPUT
entropy_i[29]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[30]	No	No		No		INPUT
entropy_i[32:31]	Yes	Yes	*T119,*T133	Yes	T119,T133	INPUT
entropy_i[34:33]	No	No		No		INPUT
entropy_i[36:35]	Yes	Yes	T119,*T133	Yes	T119,T133	INPUT
entropy_i[37]	No	No		No		INPUT
entropy_i[38]	Yes	Yes	*T119	Yes	T119	INPUT
entropy_i[39]	No	No		No		INPUT
state_o[39:0]	Yes	Yes	T10,T4,T5	Yes	T9,T10,T4	OUTPUT

*Tests covering at least one bit in the range