Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.23	94.16	96.15	97.24		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	509970719	8747190	0	0
check_regwen_rd_A	509970719	3677	0	0
check_timeout_rd_A	509970719	3329	0	0
check_trigger_regwen_rd_A	509970719	3702	0	0
consistency_check_period_rd_A	509970719	3788	0	0
creator_sw_cfg_read_lock_rd_A	509970719	3267	0	0
direct_access_address_rd_A	509970719	2694	0	0
direct_access_wdata_0_rd_A	509970719	1775	0	0
direct_access_wdata_1_rd_A	509970719	2229	0	0
integrity_check_period_rd_A	509970719	3640	0	0
intr_enable_rd_A	509970719	4548	0	0
owner_sw_cfg_read_lock_rd_A	509970719	2879	0	0
rot_creator_auth_codesign_read_lock_rd_A	509970719	3275	0	0
rot_creator_auth_state_read_lock_rd_A	509970719	3021	0	0
vendor_test_read_lock_rd_A	509970719	3122	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	8747190	0	0
T6	152790	44801	0	0
T7	259183	30863	0	0
T8	68793	0	0	0
T14	0	341215	0	0
T19	0	137096	0	0
T20	0	201718	0	0
T21	0	102013	0	0
T58	14552	0	0	0
T70	16545	0	0	0
T75	56550	0	0	0
T80	10064	0	0	0
T134	12195	0	0	0
T135	0	330056	0	0
T173	5846	0	0	0
T175	62435	0	0	0
T224	0	69972	0	0
T253	0	36367	0	0
T277	0	23909	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	3677	0	0
T21	857570	73	0	0
T22	0	106	0	0
T35	17139	0	0	0
T109	48985	0	0	0
T163	11294	0	0	0
T164	13014	0	0	0
T232	0	119	0	0
T253	0	50	0	0
T254	0	107	0	0
T267	35384	0	0	0
T280	0	110	0	0
T324	0	82	0	0
T325	0	59	0	0
T326	0	59	0	0
T327	0	94	0	0
T328	5884	0	0	0
T329	4873	0	0	0
T330	46823	0	0	0
T331	18838	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	3329	0	0
T21	857570	81	0	0
T22	0	102	0	0
T35	17139	0	0	0
T109	48985	0	0	0
T163	11294	0	0	0
T164	13014	0	0	0
T232	0	106	0	0
T253	0	59	0	0
T254	0	144	0	0
T267	35384	0	0	0
T280	0	101	0	0
T324	0	109	0	0
T325	0	52	0	0
T326	0	87	0	0
T327	0	82	0	0
T328	5884	0	0	0
T329	4873	0	0	0
T330	46823	0	0	0
T331	18838	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	3702	0	0
T21	857570	62	0	0
T22	0	132	0	0
T35	17139	0	0	0
T109	48985	0	0	0
T163	11294	0	0	0
T164	13014	0	0	0
T232	0	100	0	0
T253	0	61	0	0
T254	0	94	0	0
T267	35384	0	0	0
T280	0	89	0	0
T324	0	88	0	0
T325	0	51	0	0
T326	0	63	0	0
T327	0	76	0	0
T328	5884	0	0	0
T329	4873	0	0	0
T330	46823	0	0	0
T331	18838	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	3788	0	0
T21	857570	43	0	0
T22	0	91	0	0
T35	17139	0	0	0
T109	48985	0	0	0
T163	11294	0	0	0
T164	13014	0	0	0
T232	0	116	0	0
T253	0	47	0	0
T254	0	90	0	0
T267	35384	0	0	0
T280	0	60	0	0
T324	0	128	0	0
T325	0	65	0	0
T326	0	112	0	0
T327	0	57	0	0
T328	5884	0	0	0
T329	4873	0	0	0
T330	46823	0	0	0
T331	18838	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	3267	0	0
T21	857570	79	0	0
T22	0	143	0	0
T35	17139	0	0	0
T109	48985	0	0	0
T163	11294	0	0	0
T164	13014	0	0	0
T232	0	134	0	0
T253	0	61	0	0
T254	0	84	0	0
T267	35384	0	0	0
T280	0	100	0	0
T324	0	110	0	0
T325	0	44	0	0
T326	0	66	0	0
T327	0	112	0	0
T328	5884	0	0	0
T329	4873	0	0	0
T330	46823	0	0	0
T331	18838	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	2694	0	0
T21	857570	77	0	0
T22	0	135	0	0
T35	17139	0	0	0
T109	48985	0	0	0
T163	11294	0	0	0
T164	13014	0	0	0
T232	0	109	0	0
T253	0	70	0	0
T254	0	109	0	0
T267	35384	0	0	0
T280	0	78	0	0
T324	0	151	0	0
T325	0	97	0	0
T326	0	81	0	0
T327	0	55	0	0
T328	5884	0	0	0
T329	4873	0	0	0
T330	46823	0	0	0
T331	18838	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	1775	0	0
T21	857570	20	0	0
T22	0	84	0	0
T35	17139	0	0	0
T109	48985	0	0	0
T163	11294	0	0	0
T164	13014	0	0	0
T232	0	92	0	0
T253	0	29	0	0
T254	0	58	0	0
T267	35384	0	0	0
T280	0	67	0	0
T324	0	93	0	0
T325	0	71	0	0
T326	0	61	0	0
T327	0	95	0	0
T328	5884	0	0	0
T329	4873	0	0	0
T330	46823	0	0	0
T331	18838	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	2229	0	0
T21	857570	56	0	0
T22	0	107	0	0
T35	17139	0	0	0
T109	48985	0	0	0
T163	11294	0	0	0
T164	13014	0	0	0
T232	0	94	0	0
T253	0	42	0	0
T254	0	87	0	0
T267	35384	0	0	0
T280	0	81	0	0
T324	0	84	0	0
T325	0	80	0	0
T326	0	97	0	0
T327	0	82	0	0
T328	5884	0	0	0
T329	4873	0	0	0
T330	46823	0	0	0
T331	18838	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	3640	0	0
T21	857570	79	0	0
T22	0	64	0	0
T35	17139	0	0	0
T109	48985	0	0	0
T163	11294	0	0	0
T164	13014	0	0	0
T232	0	129	0	0
T253	0	41	0	0
T254	0	95	0	0
T267	35384	0	0	0
T280	0	129	0	0
T324	0	116	0	0
T325	0	44	0	0
T326	0	87	0	0
T327	0	84	0	0
T328	5884	0	0	0
T329	4873	0	0	0
T330	46823	0	0	0
T331	18838	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	4548	0	0
T6	152790	0	0	0
T7	259183	0	0	0
T17	136423	25	0	0
T18	5343	0	0	0
T21	0	60	0	0
T51	13634	0	0	0
T58	14552	0	0	0
T70	16545	0	0	0
T111	27809	0	0	0
T113	6774	0	0	0
T126	0	37	0	0
T173	5846	0	0	0
T220	0	34	0	0
T231	0	44	0	0
T232	0	129	0	0
T253	0	43	0	0
T254	0	69	0	0
T324	0	125	0	0
T325	0	76	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	2879	0	0
T21	857570	47	0	0
T22	0	98	0	0
T35	17139	0	0	0
T109	48985	0	0	0
T163	11294	0	0	0
T164	13014	0	0	0
T232	0	88	0	0
T253	0	42	0	0
T254	0	71	0	0
T267	35384	0	0	0
T280	0	100	0	0
T324	0	97	0	0
T325	0	61	0	0
T326	0	66	0	0
T327	0	49	0	0
T328	5884	0	0	0
T329	4873	0	0	0
T330	46823	0	0	0
T331	18838	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	3275	0	0
T21	857570	86	0	0
T22	0	138	0	0
T35	17139	0	0	0
T109	48985	0	0	0
T163	11294	0	0	0
T164	13014	0	0	0
T232	0	83	0	0
T253	0	66	0	0
T254	0	77	0	0
T267	35384	0	0	0
T280	0	104	0	0
T324	0	127	0	0
T325	0	45	0	0
T326	0	79	0	0
T327	0	80	0	0
T328	5884	0	0	0
T329	4873	0	0	0
T330	46823	0	0	0
T331	18838	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	3021	0	0
T21	857570	45	0	0
T22	0	138	0	0
T35	17139	0	0	0
T109	48985	0	0	0
T163	11294	0	0	0
T164	13014	0	0	0
T232	0	90	0	0
T253	0	27	0	0
T254	0	96	0	0
T267	35384	0	0	0
T280	0	93	0	0
T324	0	99	0	0
T325	0	64	0	0
T326	0	73	0	0
T327	0	60	0	0
T328	5884	0	0	0
T329	4873	0	0	0
T330	46823	0	0	0
T331	18838	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509970719	3122	0	0
T21	857570	52	0	0
T22	0	79	0	0
T35	17139	0	0	0
T109	48985	0	0	0
T163	11294	0	0	0
T164	13014	0	0	0
T232	0	112	0	0
T253	0	39	0	0
T254	0	134	0	0
T267	35384	0	0	0
T280	0	77	0	0
T324	0	101	0	0
T325	0	42	0	0
T326	0	88	0	0
T327	0	85	0	0
T328	5884	0	0	0
T329	4873	0	0	0
T330	46823	0	0	0
T331	18838	0	0	0