Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.85 96.55 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.85 96.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_generic_ram_1p
Line No.TotalCoveredPercent
TOTAL292896.55
CONT_ASSIGN42100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 22 22
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Module : prim_generic_ram_1p
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


Assert Coverage for Module : prim_generic_ram_1p
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 23 23 100.00 23 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 23 23 100.00 23 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 1153 1153 0 0
gen_wmask[0].MaskCheck_A 506789242 760359 0 0
gen_wmask[10].MaskCheck_A 506789242 760359 0 0
gen_wmask[11].MaskCheck_A 506789242 760359 0 0
gen_wmask[12].MaskCheck_A 506789242 760359 0 0
gen_wmask[13].MaskCheck_A 506789242 760359 0 0
gen_wmask[14].MaskCheck_A 506789242 760359 0 0
gen_wmask[15].MaskCheck_A 506789242 760359 0 0
gen_wmask[16].MaskCheck_A 506789242 760359 0 0
gen_wmask[17].MaskCheck_A 506789242 760359 0 0
gen_wmask[18].MaskCheck_A 506789242 760359 0 0
gen_wmask[19].MaskCheck_A 506789242 760359 0 0
gen_wmask[1].MaskCheck_A 506789242 760359 0 0
gen_wmask[20].MaskCheck_A 506789242 760359 0 0
gen_wmask[21].MaskCheck_A 506789242 760359 0 0
gen_wmask[2].MaskCheck_A 506789242 760359 0 0
gen_wmask[3].MaskCheck_A 506789242 760359 0 0
gen_wmask[4].MaskCheck_A 506789242 760359 0 0
gen_wmask[5].MaskCheck_A 506789242 760359 0 0
gen_wmask[6].MaskCheck_A 506789242 760359 0 0
gen_wmask[7].MaskCheck_A 506789242 760359 0 0
gen_wmask[8].MaskCheck_A 506789242 760359 0 0
gen_wmask[9].MaskCheck_A 506789242 760359 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[10].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[11].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[12].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[13].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[14].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[15].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[16].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[17].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[18].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[19].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[1].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[20].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[21].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[2].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[3].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[4].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[5].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[6].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[7].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[8].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

gen_wmask[9].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506789242 760359 0 0
T1 10801 64 0 0
T2 66604 202 0 0
T3 10510 78 0 0
T4 46824 192 0 0
T5 120327 434 0 0
T9 5172 0 0 0
T10 16500 102 0 0
T11 15126 92 0 0
T12 13669 20 0 0
T13 10762 66 0 0
T31 0 62 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%