Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
83.33	69.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
buf_err_code_cg_wrap[OtpSecret0ErrIdx]	0.00	1	100	1	64	64
buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]	83.33	1	100	1	64	64

---

Group Instance : buf_err_code_cg_wrap[OtpSecret0ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpSecret0ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	6	0	0.00

Variables for Group Instance buf_err_code_cg_wrap[OtpSecret0ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	6	0	0.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	6	0	0.00

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fsm_err	0	1	1
check_fail	0	1	1
ecc_uncorr_err	0	1	1
ecc_corr_err	0	1	1
macro_err	0	1	1
no_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	117976	1			T1	76		T3	1		T5	53
check_fail	5	1			T71	1		T72	1		T73	1
ecc_uncorr_err	109	1			T28	1		T86	1		T130	1
ecc_corr_err	151	1			T68	53		T69	57		T70	41
no_err	166772	1			T1	13		T2	98		T4	696

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	117886	1			T1	76		T5	53		T9	439
check_fail	1	1			T12	1		-	-		-	-
ecc_uncorr_err	178	1			T65	12		T87	90		T49	65
ecc_corr_err	191	1			T43	6		T44	39		T45	78
no_err	166633	1			T1	13		T2	98		T4	696

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	117925	1			T1	76		T5	53		T9	439
check_fail	13	1			T33	1		T34	1		T35	1
ecc_uncorr_err	162	1			T54	1		T47	1		T116	1
ecc_corr_err	202	1			T30	45		T31	73		T32	69
no_err	167060	1			T1	13		T2	98		T4	696

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	117968	1			T1	76		T5	53		T9	439
check_fail	38	1			T51	1		T52	1		T53	1
ecc_uncorr_err	60	1			T3	1		T120	1		T121	1
ecc_corr_err	241	1			T49	63		T50	32		T31	66
no_err	166904	1			T1	13		T2	98		T4	696

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	117644	1			T1	76		T5	53		T9	439
check_fail	22	1			T59	1		T60	1		T61	1
ecc_uncorr_err	416	1			T57	35		T85	1		T122	37
ecc_corr_err	122	1			T56	42		T57	29		T58	51
no_err	166914	1			T1	13		T2	98		T4	696