SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
85.71 | 77.14 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
unbuf_err_code_cg_wrap[OtpVendorTestErrIdx] | 57.14 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx] | 71.43 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
57.14 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 3 | 4 | 57.14 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 3 | 4 | 57.14 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
71.43 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 2 | 5 | 71.43 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 2 | 5 | 71.43 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 3 | 4 | 57.14 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
ecc_uncorr_err | 0 | 1 | 1 | |
ecc_corr_err | 0 | 1 | 1 | |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 117914 | 1 | T1 | 76 | T5 | 53 | T9 | 439 | ||||
check_fail | 2 | 1 | T84 | 1 | T138 | 1 | - | - | ||||
access_err | 59663 | 1 | T4 | 258 | T13 | 220 | T6 | 898 | ||||
no_err | 108190 | 1 | T1 | 13 | T2 | 98 | T4 | 438 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 2 | 5 | 71.43 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
check_fail | 0 | 1 | 1 | |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 117513 | 1 | T1 | 76 | T5 | 53 | T9 | 439 | ||||
access_err | 60279 | 1 | T2 | 50 | T4 | 188 | T11 | 10 | ||||
ecc_uncorr_err | 513 | 1 | T143 | 1 | T186 | 1 | T187 | 1 | ||||
ecc_corr_err | 1415 | 1 | T65 | 6 | T74 | 24 | T104 | 100 | ||||
no_err | 105768 | 1 | T1 | 13 | T2 | 48 | T4 | 508 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 117464 | 1 | T1 | 76 | T5 | 53 | T9 | 439 | ||||
check_fail | 3 | 1 | T84 | 1 | T140 | 1 | T138 | 1 | ||||
access_err | 58589 | 1 | T2 | 15 | T4 | 235 | T13 | 244 | ||||
ecc_uncorr_err | 556 | 1 | T114 | 1 | T142 | 1 | T159 | 1 | ||||
ecc_corr_err | 893 | 1 | T128 | 24 | T57 | 52 | T139 | 1 | ||||
no_err | 108238 | 1 | T1 | 13 | T2 | 83 | T4 | 461 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 117694 | 1 | T1 | 76 | T3 | 1 | T9 | 439 | ||||
check_fail | 2 | 1 | T84 | 1 | T140 | 1 | - | - | ||||
access_err | 59375 | 1 | T2 | 22 | T4 | 176 | T13 | 282 | ||||
ecc_uncorr_err | 322 | 1 | T5 | 53 | T158 | 1 | T160 | 1 | ||||
ecc_corr_err | 956 | 1 | T10 | 6 | T65 | 2 | T74 | 42 | ||||
no_err | 107258 | 1 | T1 | 13 | T2 | 76 | T4 | 520 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 117579 | 1 | T1 | 76 | T5 | 53 | T9 | 439 | ||||
check_fail | 2 | 1 | T83 | 1 | T84 | 1 | - | - | ||||
access_err | 58814 | 1 | T2 | 22 | T4 | 310 | T13 | 278 | ||||
ecc_uncorr_err | 441 | 1 | T119 | 1 | T196 | 1 | T202 | 1 | ||||
ecc_corr_err | 1089 | 1 | T104 | 13 | T57 | 10 | T141 | 1 | ||||
no_err | 107469 | 1 | T1 | 13 | T2 | 76 | T4 | 386 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |