Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7458910	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7394770

1

T1

835

T2

858

T3

207

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8656773	1			T1	1554		T2	1884		T3	444
values[0x0]	2356726	1			T1	112		T2	129		T3	108
values[0x1]	3840181	1			T1	100		T2	105		T3	146

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4843329	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

10010351

1

T1

1035

T2

1150

T3

326

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56920	1			T1	13		T2	5		T5	9
valid_sources[0x01]	52941	1			T1	5		T2	6		T3	4
valid_sources[0x02]	51243	1			T1	9		T2	10		T3	4
valid_sources[0x03]	53587	1			T1	5		T2	10		T3	4
valid_sources[0x04]	53179	1			T1	7		T2	8		T3	1
valid_sources[0x05]	55452	1			T1	11		T2	7		T3	4
valid_sources[0x06]	53156	1			T1	5		T2	8		T3	1
valid_sources[0x07]	51870	1			T1	10		T2	4		T3	4
valid_sources[0x08]	56264	1			T1	10		T2	2		T3	3
valid_sources[0x09]	62676	1			T1	3		T2	11		T3	2
valid_sources[0x0a]	56086	1			T1	8		T2	7		T3	1
valid_sources[0x0b]	59238	1			T1	11		T2	8		T3	4
valid_sources[0x0c]	51030	1			T1	9		T2	10		T3	2
valid_sources[0x0d]	51430	1			T1	7		T2	5		T3	1
valid_sources[0x0e]	53080	1			T1	15		T2	5		T5	3
valid_sources[0x0f]	57020	1			T1	16		T2	11		T3	2
valid_sources[0x10]	55382	1			T1	5		T2	12		T3	2
valid_sources[0x11]	54119	1			T1	11		T2	3		T3	2
valid_sources[0x12]	53163	1			T1	4		T2	4		T3	3
valid_sources[0x13]	56807	1			T1	2		T2	9		T3	2
valid_sources[0x14]	52364	1			T1	10		T2	1		T5	6
valid_sources[0x15]	53898	1			T1	10		T2	10		T3	4
valid_sources[0x16]	54571	1			T1	3		T2	6		T3	1
valid_sources[0x17]	53772	1			T1	9		T2	9		T3	5
valid_sources[0x18]	60828	1			T1	16		T2	6		T3	1
valid_sources[0x19]	53438	1			T1	4		T2	7		T3	1
valid_sources[0x1a]	53993	1			T1	11		T2	8		T3	3
valid_sources[0x1b]	72126	1			T1	6		T2	10		T3	3
valid_sources[0x1c]	54265	1			T1	5		T2	11		T3	7
valid_sources[0x1d]	52848	1			T2	7		T3	3		T5	8
valid_sources[0x1e]	79991	1			T1	5		T2	8		T3	2
valid_sources[0x1f]	53237	1			T1	3		T2	11		T3	2
valid_sources[0x20]	55072	1			T1	7		T2	9		T3	5
valid_sources[0x21]	54383	1			T1	7		T2	5		T3	5
valid_sources[0x22]	52835	1			T1	4		T2	10		T3	3
valid_sources[0x23]	54871	1			T1	10		T2	7		T3	5
valid_sources[0x24]	54853	1			T1	9		T2	5		T3	5
valid_sources[0x25]	59820	1			T1	10		T2	11		T5	8
valid_sources[0x26]	54008	1			T1	5		T2	7		T3	1
valid_sources[0x27]	56887	1			T1	14		T2	5		T3	1
valid_sources[0x28]	54346	1			T1	5		T2	5		T3	2
valid_sources[0x29]	68162	1			T1	6		T2	14		T3	2
valid_sources[0x2a]	51884	1			T1	12		T2	5		T3	6
valid_sources[0x2b]	55938	1			T1	5		T2	8		T3	4
valid_sources[0x2c]	52208	1			T1	8		T2	4		T3	3
valid_sources[0x2d]	66597	1			T1	9		T2	5		T3	6
valid_sources[0x2e]	58070	1			T1	11		T2	10		T3	3
valid_sources[0x2f]	53497	1			T1	8		T2	6		T3	2
valid_sources[0x30]	54984	1			T1	6		T2	11		T3	1
valid_sources[0x31]	59880	1			T1	6		T2	3		T3	1
valid_sources[0x32]	55641	1			T1	9		T2	13		T3	2
valid_sources[0x33]	53329	1			T1	13		T2	5		T3	5
valid_sources[0x34]	53370	1			T1	3		T2	9		T3	1
valid_sources[0x35]	53634	1			T1	12		T2	4		T3	2
valid_sources[0x36]	53378	1			T1	7		T2	11		T3	4
valid_sources[0x37]	56334	1			T1	7		T2	7		T3	1
valid_sources[0x38]	52625	1			T1	3		T2	4		T3	3
valid_sources[0x39]	90780	1			T1	6		T2	8		T3	6
valid_sources[0x3a]	66002	1			T1	6		T2	14		T3	3
valid_sources[0x3b]	66751	1			T1	9		T2	4		T3	2
valid_sources[0x3c]	53104	1			T1	5		T2	8		T3	4
valid_sources[0x3d]	62916	1			T1	6		T2	7		T3	3
valid_sources[0x3e]	54070	1			T1	12		T2	6		T3	1
valid_sources[0x3f]	60169	1			T1	3		T2	9		T3	1
valid_sources[0x40]	54508	1			T1	13		T2	5		T3	10
valid_sources[0x41]	126011	1			T1	9		T2	7		T5	6
valid_sources[0x42]	57035	1			T1	5		T2	6		T3	2
valid_sources[0x43]	54142	1			T1	9		T2	8		T5	6
valid_sources[0x44]	52800	1			T1	5		T2	7		T3	2
valid_sources[0x45]	59800	1			T1	5		T2	6		T3	1
valid_sources[0x46]	54126	1			T1	9		T2	5		T3	4
valid_sources[0x47]	52485	1			T1	5		T2	6		T3	2
valid_sources[0x48]	63577	1			T1	2		T2	8		T3	5
valid_sources[0x49]	64999	1			T1	7		T2	12		T3	5
valid_sources[0x4a]	58728	1			T1	8		T2	7		T3	4
valid_sources[0x4b]	55257	1			T1	1		T2	8		T3	1
valid_sources[0x4c]	53811	1			T1	15		T2	9		T3	3
valid_sources[0x4d]	52978	1			T1	7		T2	9		T3	3
valid_sources[0x4e]	66234	1			T1	10		T2	6		T3	4
valid_sources[0x4f]	52289	1			T1	2		T2	8		T3	3
valid_sources[0x50]	53500	1			T1	11		T2	5		T3	5
valid_sources[0x51]	54643	1			T1	11		T2	8		T3	2
valid_sources[0x52]	54575	1			T1	3		T2	7		T3	3
valid_sources[0x53]	51604	1			T1	5		T2	2		T3	1
valid_sources[0x54]	51700	1			T1	11		T2	6		T3	2
valid_sources[0x55]	55352	1			T1	2		T2	7		T3	2
valid_sources[0x56]	55471	1			T1	7		T2	8		T3	5
valid_sources[0x57]	53264	1			T1	8		T2	5		T3	6
valid_sources[0x58]	54340	1			T1	3		T2	12		T3	3
valid_sources[0x59]	54952	1			T1	10		T2	10		T3	1
valid_sources[0x5a]	52535	1			T1	6		T2	12		T3	6
valid_sources[0x5b]	62384	1			T1	5		T2	16		T3	5
valid_sources[0x5c]	54541	1			T1	4		T2	7		T3	2
valid_sources[0x5d]	60690	1			T1	10		T2	6		T5	12
valid_sources[0x5e]	152516	1			T1	5		T2	7		T3	2
valid_sources[0x5f]	51352	1			T1	6		T2	14		T3	2
valid_sources[0x60]	52952	1			T1	15		T2	12		T3	2
valid_sources[0x61]	53124	1			T1	8		T2	8		T3	2
valid_sources[0x62]	61646	1			T1	3		T2	7		T5	6
valid_sources[0x63]	52954	1			T1	3		T2	9		T3	4
valid_sources[0x64]	66643	1			T1	5		T2	6		T3	2
valid_sources[0x65]	54618	1			T1	5		T2	10		T5	8
valid_sources[0x66]	51074	1			T1	13		T2	11		T3	1
valid_sources[0x67]	53625	1			T1	5		T2	5		T3	1
valid_sources[0x68]	53776	1			T1	4		T2	7		T5	10
valid_sources[0x69]	53231	1			T1	5		T2	7		T3	3
valid_sources[0x6a]	57707	1			T1	10		T2	12		T3	1
valid_sources[0x6b]	53681	1			T1	3		T2	7		T3	1
valid_sources[0x6c]	53159	1			T1	4		T2	9		T3	4
valid_sources[0x6d]	55088	1			T1	8		T2	4		T3	4
valid_sources[0x6e]	55268	1			T1	4		T2	15		T5	8
valid_sources[0x6f]	54525	1			T1	8		T2	11		T3	3
valid_sources[0x70]	55034	1			T1	9		T2	9		T3	2
valid_sources[0x71]	52996	1			T1	6		T2	9		T3	3
valid_sources[0x72]	53821	1			T1	3		T2	7		T3	3
valid_sources[0x73]	52053	1			T1	9		T2	14		T3	5
valid_sources[0x74]	53552	1			T1	6		T2	11		T3	2
valid_sources[0x75]	55511	1			T1	4		T2	6		T3	6
valid_sources[0x76]	51576	1			T1	8		T2	4		T3	3
valid_sources[0x77]	56417	1			T1	8		T2	13		T3	3
valid_sources[0x78]	54166	1			T1	3		T2	2		T3	2
valid_sources[0x79]	55426	1			T1	4		T2	6		T3	2
valid_sources[0x7a]	56506	1			T1	3		T2	6		T3	7
valid_sources[0x7b]	60158	1			T1	4		T2	11		T3	5
valid_sources[0x7c]	58215	1			T1	2		T2	10		T3	1
valid_sources[0x7d]	57077	1			T1	16		T2	6		T3	2
valid_sources[0x7e]	55915	1			T1	6		T2	9		T3	2
valid_sources[0x7f]	53893	1			T1	3		T2	9		T3	2
valid_sources[0x80]	56354	1			T1	17		T2	3		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3562908

1

T1

733

T2

760

T3

98

values[0x0]

all_enables

biggest_size

1953769

1

T1

56

T2

65

T3

54

values[0x1]

all_enables

biggest_size

1878093

1

T1

46

T2

33

T3

55

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	251928	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9165900

1

T1

160

T2

40

T4

200

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2342617	1			T1	80		T2	20		T4	100
values[0x0]	3435694	1			T1	44		T2	9		T4	50
values[0x1]	3639517	1			T1	36		T2	11		T4	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	90227	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9327601

1

T1

160

T2

40

T4

200

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	36051	1			T1	1		T6	756		T7	625
valid_sources[0x01]	36769	1			T6	781		T7	572		T8	1302
valid_sources[0x02]	35051	1			T9	1		T6	782		T108	29
valid_sources[0x03]	37083	1			T6	649		T7	542		T8	1316
valid_sources[0x04]	37207	1			T9	1		T6	790		T7	540
valid_sources[0x05]	35202	1			T9	2		T13	5		T6	732
valid_sources[0x06]	36311	1			T29	3		T6	754		T7	541
valid_sources[0x07]	36334	1			T9	1		T13	3		T6	781
valid_sources[0x08]	36974	1			T9	1		T6	762		T7	620
valid_sources[0x09]	38107	1			T29	2		T6	707		T7	506
valid_sources[0x0a]	36610	1			T9	1		T6	714		T7	500
valid_sources[0x0b]	37187	1			T4	7		T11	2		T13	2
valid_sources[0x0c]	36296	1			T1	8		T9	1		T13	2
valid_sources[0x0d]	34629	1			T6	856		T7	511		T8	1179
valid_sources[0x0e]	37488	1			T4	2		T9	1		T6	750
valid_sources[0x0f]	37555	1			T11	1		T6	821		T7	546
valid_sources[0x10]	35923	1			T4	1		T6	798		T7	612
valid_sources[0x11]	37490	1			T4	4		T29	1		T6	707
valid_sources[0x12]	38233	1			T2	2		T9	1		T13	1
valid_sources[0x13]	36824	1			T9	2		T6	684		T7	559
valid_sources[0x14]	34573	1			T1	1		T6	731		T108	8
valid_sources[0x15]	35838	1			T9	1		T6	801		T7	512
valid_sources[0x16]	36152	1			T4	8		T6	745		T7	631
valid_sources[0x17]	36687	1			T4	6		T9	3		T11	1
valid_sources[0x18]	35988	1			T9	2		T6	741		T108	4
valid_sources[0x19]	37201	1			T4	12		T6	798		T7	580
valid_sources[0x1a]	37175	1			T6	702		T7	577		T8	1239
valid_sources[0x1b]	36194	1			T1	1		T4	7		T9	1
valid_sources[0x1c]	37133	1			T6	746		T7	546		T8	1298
valid_sources[0x1d]	37001	1			T9	3		T6	709		T7	602
valid_sources[0x1e]	37232	1			T9	1		T13	1		T6	720
valid_sources[0x1f]	37070	1			T11	1		T13	2		T29	8
valid_sources[0x20]	37624	1			T1	1		T6	795		T7	569
valid_sources[0x21]	36299	1			T13	1		T6	846		T7	487
valid_sources[0x22]	37910	1			T9	1		T13	1		T6	694
valid_sources[0x23]	36340	1			T9	1		T6	809		T7	605
valid_sources[0x24]	36098	1			T4	1		T6	733		T7	509
valid_sources[0x25]	36213	1			T6	801		T7	520		T8	1274
valid_sources[0x26]	36416	1			T13	2		T6	773		T7	564
valid_sources[0x27]	37874	1			T4	5		T9	1		T6	692
valid_sources[0x28]	37158	1			T13	1		T6	771		T7	474
valid_sources[0x29]	36648	1			T9	1		T6	780		T108	4
valid_sources[0x2a]	36348	1			T1	7		T9	2		T6	719
valid_sources[0x2b]	37413	1			T6	766		T7	555		T8	1297
valid_sources[0x2c]	36862	1			T6	808		T7	545		T8	1318
valid_sources[0x2d]	39129	1			T9	1		T13	1		T6	762
valid_sources[0x2e]	35615	1			T29	5		T6	767		T7	533
valid_sources[0x2f]	35296	1			T1	4		T9	1		T13	1
valid_sources[0x30]	36344	1			T6	738		T7	567		T8	1214
valid_sources[0x31]	35885	1			T1	1		T11	1		T29	2
valid_sources[0x32]	36571	1			T1	1		T13	1		T6	783
valid_sources[0x33]	39215	1			T1	8		T6	710		T7	590
valid_sources[0x34]	35705	1			T9	1		T6	707		T7	569
valid_sources[0x35]	37600	1			T1	2		T5	1		T9	2
valid_sources[0x36]	37269	1			T11	2		T6	646		T108	18
valid_sources[0x37]	38614	1			T9	2		T13	5		T6	741
valid_sources[0x38]	35749	1			T1	3		T4	1		T29	1
valid_sources[0x39]	35553	1			T13	3		T6	718		T7	567
valid_sources[0x3a]	37481	1			T6	786		T7	563		T8	1227
valid_sources[0x3b]	37528	1			T5	3		T9	3		T6	713
valid_sources[0x3c]	38190	1			T9	1		T6	686		T7	576
valid_sources[0x3d]	36183	1			T13	1		T6	775		T7	524
valid_sources[0x3e]	37499	1			T6	728		T7	483		T8	1258
valid_sources[0x3f]	36884	1			T13	3		T29	5		T6	877
valid_sources[0x40]	34572	1			T6	825		T7	532		T8	1310
valid_sources[0x41]	38240	1			T4	3		T9	1		T6	850
valid_sources[0x42]	36400	1			T9	2		T6	717		T7	607
valid_sources[0x43]	36900	1			T13	2		T6	730		T7	537
valid_sources[0x44]	37785	1			T6	615		T7	621		T8	1325
valid_sources[0x45]	38137	1			T9	1		T13	1		T6	756
valid_sources[0x46]	37671	1			T4	3		T13	1		T29	11
valid_sources[0x47]	35642	1			T13	3		T6	823		T7	533
valid_sources[0x48]	36088	1			T1	1		T9	1		T11	1
valid_sources[0x49]	36863	1			T4	4		T9	1		T13	1
valid_sources[0x4a]	37038	1			T9	2		T6	758		T7	508
valid_sources[0x4b]	37213	1			T9	1		T6	695		T7	543
valid_sources[0x4c]	38028	1			T13	1		T6	813		T7	541
valid_sources[0x4d]	35205	1			T9	3		T6	796		T7	491
valid_sources[0x4e]	34345	1			T4	17		T6	882		T7	588
valid_sources[0x4f]	35280	1			T1	9		T11	1		T6	729
valid_sources[0x50]	37344	1			T9	2		T6	726		T7	566
valid_sources[0x51]	36348	1			T6	726		T7	594		T8	1227
valid_sources[0x52]	38122	1			T4	7		T9	2		T13	3
valid_sources[0x53]	37179	1			T13	1		T6	710		T7	482
valid_sources[0x54]	37365	1			T9	1		T13	2		T6	781
valid_sources[0x55]	35927	1			T13	1		T6	690		T7	550
valid_sources[0x56]	37196	1			T4	3		T5	1		T9	1
valid_sources[0x57]	37024	1			T9	2		T6	737		T7	496
valid_sources[0x58]	36575	1			T4	2		T9	1		T6	764
valid_sources[0x59]	35854	1			T9	2		T6	739		T7	589
valid_sources[0x5a]	36485	1			T13	1		T6	801		T7	536
valid_sources[0x5b]	37587	1			T6	742		T7	528		T8	1261
valid_sources[0x5c]	36780	1			T1	1		T6	781		T108	3
valid_sources[0x5d]	37660	1			T13	1		T6	718		T7	548
valid_sources[0x5e]	37552	1			T9	1		T6	715		T108	5
valid_sources[0x5f]	38357	1			T9	2		T6	734		T7	560
valid_sources[0x60]	37399	1			T6	810		T7	445		T8	1317
valid_sources[0x61]	38248	1			T6	729		T108	15		T7	636
valid_sources[0x62]	38974	1			T4	2		T5	2		T9	1
valid_sources[0x63]	35242	1			T1	2		T4	4		T13	1
valid_sources[0x64]	37784	1			T1	2		T9	1		T6	828
valid_sources[0x65]	36992	1			T5	1		T9	1		T13	1
valid_sources[0x66]	35375	1			T6	776		T7	549		T8	1267
valid_sources[0x67]	35494	1			T6	676		T7	581		T8	1311
valid_sources[0x68]	37096	1			T9	4		T11	2		T6	754
valid_sources[0x69]	35459	1			T1	1		T6	818		T7	562
valid_sources[0x6a]	37898	1			T9	2		T13	2		T6	822
valid_sources[0x6b]	37410	1			T9	1		T6	746		T7	574
valid_sources[0x6c]	36693	1			T6	723		T7	625		T8	1294
valid_sources[0x6d]	37495	1			T6	774		T7	612		T8	1282
valid_sources[0x6e]	37521	1			T13	2		T6	733		T7	560
valid_sources[0x6f]	35237	1			T6	751		T7	583		T8	1332
valid_sources[0x70]	37147	1			T1	3		T6	640		T7	579
valid_sources[0x71]	36472	1			T4	5		T6	773		T7	625
valid_sources[0x72]	36062	1			T9	1		T13	2		T6	804
valid_sources[0x73]	38584	1			T1	14		T9	1		T13	2
valid_sources[0x74]	35037	1			T9	1		T13	1		T6	760
valid_sources[0x75]	36134	1			T4	11		T6	780		T7	549
valid_sources[0x76]	36639	1			T6	684		T7	546		T8	1278
valid_sources[0x77]	36470	1			T9	1		T13	1		T6	744
valid_sources[0x78]	37224	1			T1	1		T4	2		T13	2
valid_sources[0x79]	37458	1			T1	2		T13	4		T6	790
valid_sources[0x7a]	37320	1			T9	3		T29	3		T6	736
valid_sources[0x7b]	34770	1			T6	708		T7	618		T8	1299
valid_sources[0x7c]	37043	1			T13	2		T29	1		T6	733
valid_sources[0x7d]	35440	1			T9	1		T13	1		T6	766
valid_sources[0x7e]	36137	1			T9	1		T6	681		T7	548
valid_sources[0x7f]	38027	1			T29	11		T6	737		T7	566
valid_sources[0x80]	36157	1			T6	778		T7	581		T8	1248

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2330511

1

T1

80

T2

20

T4

100

values[0x0]

all_enables

biggest_size

3418597

1

T1

44

T2

9

T4

50

values[0x1]

all_enables

biggest_size

3416792

1

T1

36

T2

11

T4

50