Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25842229

1

T1

931

T2

1260

T3

491

full_word

8508382

1

T1

835

T2

858

T3

207

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34350361	1			T1	1766		T2	2118		T3	698
auto[TlIntgErrCmd]	83	1			T262	3		T263	3		T264	4
auto[TlIntgErrData]	78	1			T262	4		T263	1		T264	3
auto[TlIntgErrBoth]	89	1			T262	3		T263	6		T264	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10005586

1

T1

1554

T2

1884

T3

444

auto[1]

24345025

1

T1

212

T2

234

T3

254

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6305536	1			T1	821		T2	1124		T3	346
auto[TlIntgErrNone]	partial	auto[1]	19536469	1			T1	110		T2	136		T3	145
auto[TlIntgErrNone]	full_word	auto[0]	3699931	1			T1	733		T2	760		T3	98
auto[TlIntgErrNone]	full_word	auto[1]	4808425	1			T1	102		T2	98		T3	109
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T262	2		T263	1		T264	2
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T262	1		T263	1		T264	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T263	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T340	1		T341	3		T342	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T262	2		T263	1		T264	3
auto[TlIntgErrData]	partial	auto[1]	28	1			T262	1		T335	4		T266	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T343	1		T344	1		T342	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T262	1		T335	2		T339	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T263	3		T264	2		T335	3
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T262	3		T263	3		T264	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T344	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T341	1		T345	1		T346	1