Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.10		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	476897580	8270960	0	0
check_regwen_rd_A	476897580	3485	0	0
check_timeout_rd_A	476897580	3053	0	0
check_trigger_regwen_rd_A	476897580	3354	0	0
consistency_check_period_rd_A	476897580	3702	0	0
creator_sw_cfg_read_lock_rd_A	476897580	3091	0	0
direct_access_address_rd_A	476897580	2016	0	0
direct_access_wdata_0_rd_A	476897580	1465	0	0
direct_access_wdata_1_rd_A	476897580	1484	0	0
integrity_check_period_rd_A	476897580	3365	0	0
intr_enable_rd_A	476897580	3938	0	0
owner_sw_cfg_read_lock_rd_A	476897580	2916	0	0
rot_creator_auth_codesign_read_lock_rd_A	476897580	3113	0	0
rot_creator_auth_state_read_lock_rd_A	476897580	2799	0	0
vendor_test_read_lock_rd_A	476897580	2618	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	8270960	0	0
T6	112716	163625	0	0
T7	637057	124021	0	0
T8	111916	292392	0	0
T15	0	162580	0	0
T16	20311	0	0	0
T17	0	51576	0	0
T18	0	120035	0	0
T33	16168	0	0	0
T39	0	188758	0	0
T40	0	54838	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T77	0	46080	0	0
T108	10168	0	0	0
T174	0	89249	0	0
T232	88626	0	0	0
T267	36607	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	3485	0	0
T6	112716	150	0	0
T7	637057	154	0	0
T8	111916	0	0	0
T16	20311	0	0	0
T20	0	49	0	0
T33	16168	0	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T108	10168	0	0	0
T232	88626	0	0	0
T267	36607	0	0	0
T271	0	82	0	0
T313	0	81	0	0
T314	0	168	0	0
T315	0	98	0	0
T316	0	33	0	0
T317	0	135	0	0
T318	0	139	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	3053	0	0
T6	112716	251	0	0
T7	637057	168	0	0
T8	111916	0	0	0
T16	20311	0	0	0
T20	0	52	0	0
T33	16168	0	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T108	10168	0	0	0
T232	88626	0	0	0
T267	36607	0	0	0
T271	0	78	0	0
T313	0	84	0	0
T314	0	188	0	0
T315	0	117	0	0
T316	0	23	0	0
T317	0	99	0	0
T318	0	99	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	3354	0	0
T6	112716	145	0	0
T7	637057	155	0	0
T8	111916	0	0	0
T16	20311	0	0	0
T20	0	51	0	0
T33	16168	0	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T108	10168	0	0	0
T232	88626	0	0	0
T267	36607	0	0	0
T271	0	83	0	0
T313	0	61	0	0
T314	0	171	0	0
T315	0	109	0	0
T316	0	32	0	0
T317	0	95	0	0
T318	0	68	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	3702	0	0
T6	112716	228	0	0
T7	637057	169	0	0
T8	111916	0	0	0
T16	20311	0	0	0
T20	0	86	0	0
T33	16168	0	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T108	10168	0	0	0
T232	88626	0	0	0
T267	36607	0	0	0
T271	0	71	0	0
T313	0	96	0	0
T314	0	194	0	0
T315	0	81	0	0
T316	0	42	0	0
T317	0	165	0	0
T318	0	116	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	3091	0	0
T6	112716	262	0	0
T7	637057	180	0	0
T8	111916	0	0	0
T16	20311	0	0	0
T20	0	96	0	0
T33	16168	0	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T108	10168	0	0	0
T232	88626	0	0	0
T267	36607	0	0	0
T271	0	81	0	0
T313	0	105	0	0
T314	0	169	0	0
T315	0	116	0	0
T316	0	53	0	0
T317	0	109	0	0
T318	0	66	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	2016	0	0
T6	112716	241	0	0
T7	637057	136	0	0
T8	111916	0	0	0
T16	20311	0	0	0
T20	0	93	0	0
T33	16168	0	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T108	10168	0	0	0
T232	88626	0	0	0
T267	36607	0	0	0
T271	0	54	0	0
T313	0	29	0	0
T314	0	132	0	0
T315	0	90	0	0
T316	0	81	0	0
T317	0	187	0	0
T318	0	112	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	1465	0	0
T6	112716	136	0	0
T7	637057	163	0	0
T8	111916	0	0	0
T16	20311	0	0	0
T20	0	60	0	0
T33	16168	0	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T108	10168	0	0	0
T232	88626	0	0	0
T267	36607	0	0	0
T271	0	61	0	0
T313	0	56	0	0
T314	0	95	0	0
T315	0	52	0	0
T316	0	19	0	0
T317	0	119	0	0
T318	0	95	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	1484	0	0
T6	112716	240	0	0
T7	637057	121	0	0
T8	111916	0	0	0
T16	20311	0	0	0
T20	0	34	0	0
T33	16168	0	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T108	10168	0	0	0
T232	88626	0	0	0
T267	36607	0	0	0
T271	0	35	0	0
T313	0	69	0	0
T314	0	110	0	0
T315	0	42	0	0
T316	0	20	0	0
T317	0	107	0	0
T318	0	109	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	3365	0	0
T6	112716	178	0	0
T7	637057	109	0	0
T8	111916	0	0	0
T16	20311	0	0	0
T20	0	56	0	0
T33	16168	0	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T108	10168	0	0	0
T232	88626	0	0	0
T267	36607	0	0	0
T271	0	86	0	0
T313	0	65	0	0
T314	0	182	0	0
T315	0	111	0	0
T316	0	40	0	0
T317	0	128	0	0
T318	0	74	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	3938	0	0
T6	112716	200	0	0
T7	637057	157	0	0
T8	111916	0	0	0
T16	20311	0	0	0
T33	16168	0	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T108	10168	0	0	0
T232	88626	0	0	0
T254	0	36	0	0
T267	36607	0	0	0
T271	0	40	0	0
T313	0	110	0	0
T314	0	117	0	0
T315	0	101	0	0
T319	0	43	0	0
T320	0	4	0	0
T321	0	12	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	2916	0	0
T6	112716	215	0	0
T7	637057	162	0	0
T8	111916	0	0	0
T16	20311	0	0	0
T20	0	74	0	0
T33	16168	0	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T108	10168	0	0	0
T232	88626	0	0	0
T267	36607	0	0	0
T271	0	55	0	0
T313	0	54	0	0
T314	0	158	0	0
T315	0	93	0	0
T316	0	39	0	0
T317	0	143	0	0
T318	0	119	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	3113	0	0
T6	112716	268	0	0
T7	637057	141	0	0
T8	111916	0	0	0
T16	20311	0	0	0
T20	0	88	0	0
T33	16168	0	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T108	10168	0	0	0
T232	88626	0	0	0
T267	36607	0	0	0
T271	0	77	0	0
T313	0	46	0	0
T314	0	237	0	0
T315	0	123	0	0
T316	0	37	0	0
T317	0	104	0	0
T318	0	126	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	2799	0	0
T6	112716	158	0	0
T7	637057	193	0	0
T8	111916	0	0	0
T16	20311	0	0	0
T20	0	61	0	0
T33	16168	0	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T108	10168	0	0	0
T232	88626	0	0	0
T267	36607	0	0	0
T271	0	69	0	0
T313	0	51	0	0
T314	0	107	0	0
T315	0	55	0	0
T316	0	42	0	0
T317	0	163	0	0
T318	0	79	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476897580	2618	0	0
T6	112716	182	0	0
T7	637057	157	0	0
T8	111916	0	0	0
T16	20311	0	0	0
T20	0	52	0	0
T33	16168	0	0	0
T41	157536	0	0	0
T54	13730	0	0	0
T108	10168	0	0	0
T232	88626	0	0	0
T267	36607	0	0	0
T271	0	77	0	0
T313	0	65	0	0
T314	0	147	0	0
T315	0	95	0	0
T316	0	29	0	0
T317	0	133	0	0
T318	0	83	0	0