Module Definition
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Module Instance : tb.dut.u_prim_lc_sender_otp_broadcast_valid

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.20 94.16 96.15 97.10 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sender_test_tokens_valid

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.20 94.16 96.15 97.10 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_no_flops.gen_bits[0].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[1].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[2].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sender_rma_token_valid

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.20 94.16 96.15 97.10 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_no_flops.gen_bits[0].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[1].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[2].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sender_secrets_valid

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.20 94.16 96.15 97.10 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_no_flops.gen_bits[0].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[1].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[2].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_lc_sender ( parameter AsyncOn=1,ResetValueIsOn=0,ResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sender_otp_broadcast_valid

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
66 1 1


Line Coverage for Module : prim_lc_sender ( parameter AsyncOn=0,ResetValueIsOn=0,ResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sender_test_tokens_valid

SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sender_rma_token_valid

SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sender_secrets_valid

Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN3211100.00
ALWAYS5833100.00
CONT_ASSIGN6611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
58 1 1
59 1 1
61 1 1
66 1 1


Branch Coverage for Module : prim_lc_sender
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 58 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 58 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sender_otp_broadcast_valid
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
66 1 1

Line Coverage for Instance : tb.dut.u_prim_lc_sender_test_tokens_valid
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN3211100.00
ALWAYS5833100.00
CONT_ASSIGN6611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
58 1 1
59 1 1
61 1 1
66 1 1


Branch Coverage for Instance : tb.dut.u_prim_lc_sender_test_tokens_valid
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 58 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 58 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sender_rma_token_valid
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN3211100.00
ALWAYS5833100.00
CONT_ASSIGN6611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
58 1 1
59 1 1
61 1 1
66 1 1


Branch Coverage for Instance : tb.dut.u_prim_lc_sender_rma_token_valid
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 58 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 58 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sender_secrets_valid
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN3211100.00
ALWAYS5833100.00
CONT_ASSIGN6611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
58 1 1
59 1 1
61 1 1
66 1 1


Branch Coverage for Instance : tb.dut.u_prim_lc_sender_secrets_valid
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 58 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 58 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%