Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	100.00	100.00		85.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.73	100.00	100.00	100.00	85.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.10		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.10		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.10		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T3,T4
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T84,T138
1	Covered	T84,T138

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T5
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T181,T182,T183
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T13,T6
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T76,T83,T84
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T4,T13,T6
CheckFailError	317	Covered	T84,T138
FsmStateError	289	Covered	T1,T3,T5
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T7,T77,T39
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T4,T13,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T84,T138
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T3,T5
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T4,T13,T6
NoError->CheckFailError	317	Covered	T84,T138
NoError->FsmStateError	289	Covered	T1,T3,T5
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T6,T7,T42
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T13,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T84,T138
1	0	Covered	T84,T138
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	474290662	473403068	0	0
DigestKnown_A	474290662	473403068	0	0
DigestOffsetMustBeRepresentable_A	1151	1151	0	0
EccErrorState_A	474290662	6105	0	0
ErrorKnown_A	474290662	473403068	0	0
FsmStateKnown_A	474290662	473403068	0	0
InitDoneKnown_A	474290662	473403068	0	0
InitReadLocksPartition_A	474290662	106176859	0	0
InitWriteLocksPartition_A	474290662	106176859	0	0
OffsetMustBeBlockAligned_A	1151	1151	0	0
OtpAddrKnown_A	474290662	473403068	0	0
OtpCmdKnown_A	474290662	473403068	0	0
OtpErrorState_A	474290662	0	0	0
OtpReqKnown_A	474290662	473403068	0	0
OtpSizeKnown_A	474290662	473403068	0	0
OtpWdataKnown_A	474290662	473403068	0	0
ReadLockPropagation_A	474290662	220783824	0	0
SizeMustBeBlockAligned_A	1151	1151	0	0
TlulGntKnown_A	474290662	473403068	0	0
TlulRdataKnown_A	474290662	473403068	0	0
TlulReadOnReadLock_A	474290662	8093	0	0
TlulRerrorKnown_A	474290662	473403068	0	0
TlulRvalidKnown_A	474290662	473403068	0	0
WriteLockPropagation_A	474290662	2633599	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	474290662	30408979	0	0
u_state_regs_A	474290662	473403068	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	6105	0	0
T72	12743	0	0	0
T73	16881	0	0	0
T84	14552	2666	0	0
T138	0	3439	0	0
T151	124408	0	0	0
T152	225937	0	0	0
T153	34164	0	0	0
T154	13793	0	0	0
T155	12000	0	0	0
T156	50435	0	0	0
T157	14571	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	106176859	0	0
T1	26845	17622	0	0
T2	39407	304	0	0
T3	12374	4399	0	0
T4	198898	841	0	0
T5	12788	2185	0	0
T9	62586	55825	0	0
T10	123012	3585	0	0
T11	11727	516	0	0
T12	13617	3601	0	0
T13	190561	9311	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	106176859	0	0
T1	26845	17622	0	0
T2	39407	304	0	0
T3	12374	4399	0	0
T4	198898	841	0	0
T5	12788	2185	0	0
T9	62586	55825	0	0
T10	123012	3585	0	0
T11	11727	516	0	0
T12	13617	3601	0	0
T13	190561	9311	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	220783824	0	0
T4	198898	94414	0	0
T5	12788	0	0	0
T6	0	857712	0	0
T7	0	452570	0	0
T8	0	349837	0	0
T9	62586	0	0	0
T10	123012	0	0	0
T11	11727	2907	0	0
T12	13617	0	0	0
T13	190561	86623	0	0
T16	0	2312	0	0
T26	17862	0	0	0
T29	16856	0	0	0
T39	0	685796	0	0
T41	0	70209	0	0
T51	14587	0	0	0
T77	0	972266	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	8093	0	0
T1	26845	1	0	0
T2	39407	0	0	0
T3	12374	0	0	0
T4	198898	12	0	0
T5	12788	2	0	0
T6	0	86	0	0
T7	0	53	0	0
T9	62586	18	0	0
T10	123012	1	0	0
T11	11727	0	0	0
T12	13617	0	0	0
T13	190561	12	0	0
T29	0	1	0	0
T108	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	2633599	0	0
T4	198898	26398	0	0
T5	12788	0	0	0
T9	62586	0	0	0
T10	123012	0	0	0
T11	11727	0	0	0
T12	13617	0	0	0
T13	190561	0	0	0
T26	17862	0	0	0
T29	16856	0	0	0
T41	0	15097	0	0
T42	0	1955	0	0
T51	14587	0	0	0
T65	0	6747	0	0
T75	0	1595	0	0
T101	0	751	0	0
T103	0	10329	0	0
T104	0	9335	0	0
T105	0	5225	0	0
T111	0	3027	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	30408979	0	0
T1	26845	3446	0	0
T2	39407	24669	0	0
T3	12374	0	0	0
T4	198898	174733	0	0
T5	12788	0	0	0
T9	62586	0	0	0
T10	123012	34081	0	0
T11	11727	0	0	0
T12	13617	0	0	0
T13	190561	157773	0	0
T41	0	137785	0	0
T42	0	54765	0	0
T99	0	145772	0	0
T100	0	30135	0	0
T102	0	31445	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T36

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T128,T57,T139

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T84,T140,T138
1	Covered	T84,T140,T138

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T5
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T181,T182,T183
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T114,T142,T184
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T4,T13
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T169,T173,T185
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T76,T83,T84
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T4,T13
CheckFailError	317	Covered	T84,T140,T138
FsmStateError	289	Covered	T1,T3,T5
MacroEccCorrError	221	Covered	T26,T27,T128
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T7,T77,T39
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T4,T13
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T84,T140,T138
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T3,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T26,T27,T36
MacroEccCorrError->NoError	235	Covered	T128,T57,T30
NoError->AccessError	256	Covered	T2,T4,T13
NoError->CheckFailError	317	Covered	T84,T140,T138
NoError->FsmStateError	289	Covered	T1,T3,T5
NoError->MacroEccCorrError	221	Covered	T26,T27,T128

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T26,T27,T36
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T114,T142,T159
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T6,T7,T42
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T13
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T128,T57,T139
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T169,T173,T185
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T84,T140,T138
1	0	Covered	T84,T140,T138
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	474290662	473403068	0	0
DigestKnown_A	474290662	473403068	0	0
DigestOffsetMustBeRepresentable_A	1151	1151	0	0
EccErrorState_A	474290662	8983	0	0
ErrorKnown_A	474290662	473403068	0	0
FsmStateKnown_A	474290662	473403068	0	0
InitDoneKnown_A	474290662	473403068	0	0
InitReadLocksPartition_A	474290662	106364095	0	0
InitWriteLocksPartition_A	474290662	106364095	0	0
OffsetMustBeBlockAligned_A	1151	1151	0	0
OtpAddrKnown_A	474290662	473403068	0	0
OtpCmdKnown_A	474290662	473403068	0	0
OtpErrorState_A	474290662	62	0	0
OtpReqKnown_A	474290662	473403068	0	0
OtpSizeKnown_A	474290662	473403068	0	0
OtpWdataKnown_A	474290662	473403068	0	0
ReadLockPropagation_A	474290662	222452973	0	0
SizeMustBeBlockAligned_A	1151	1151	0	0
TlulGntKnown_A	474290662	473403068	0	0
TlulRdataKnown_A	474290662	473403068	0	0
TlulReadOnReadLock_A	474290662	8266	0	0
TlulRerrorKnown_A	474290662	473403068	0	0
TlulRvalidKnown_A	474290662	473403068	0	0
WriteLockPropagation_A	474290662	2586412	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	474290662	28772158	0	0
u_state_regs_A	474290662	473403068	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	8983	0	0
T72	12743	0	0	0
T73	16881	0	0	0
T84	14552	2666	0	0
T138	0	3439	0	0
T140	0	2878	0	0
T151	124408	0	0	0
T152	225937	0	0	0
T153	34164	0	0	0
T154	13793	0	0	0
T155	12000	0	0	0
T156	50435	0	0	0
T157	14571	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	106364095	0	0
T1	26845	17673	0	0
T2	39407	372	0	0
T3	12374	4433	0	0
T4	198898	1079	0	0
T5	12788	2236	0	0
T9	62586	55859	0	0
T10	123012	3755	0	0
T11	11727	567	0	0
T12	13617	3635	0	0
T13	190561	9498	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	106364095	0	0
T1	26845	17673	0	0
T2	39407	372	0	0
T3	12374	4433	0	0
T4	198898	1079	0	0
T5	12788	2236	0	0
T9	62586	55859	0	0
T10	123012	3755	0	0
T11	11727	567	0	0
T12	13617	3635	0	0
T13	190561	9498	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	62	0	0
T14	121021	0	0	0
T17	183139	0	0	0
T39	906415	0	0	0
T42	64012	0	0	0
T77	202155	0	0	0
T102	40098	0	0	0
T112	14233	0	0	0
T114	11774	1	0	0
T142	0	1	0	0
T159	0	1	0	0
T165	0	1	0	0
T167	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	425218	0	0	0
T175	10186	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	222452973	0	0
T2	39407	5894	0	0
T3	12374	0	0	0
T4	198898	95229	0	0
T5	12788	0	0	0
T6	0	873258	0	0
T7	0	458150	0	0
T8	0	349209	0	0
T9	62586	0	0	0
T10	123012	0	0	0
T11	11727	0	0	0
T12	13617	0	0	0
T13	190561	89408	0	0
T17	0	114053	0	0
T26	17862	0	0	0
T39	0	685089	0	0
T41	0	66354	0	0
T77	0	972004	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	8266	0	0
T1	26845	1	0	0
T2	39407	1	0	0
T3	12374	0	0	0
T4	198898	13	0	0
T5	12788	4	0	0
T6	0	83	0	0
T7	0	62	0	0
T9	62586	14	0	0
T10	123012	0	0	0
T11	11727	0	0	0
T12	13617	0	0	0
T13	190561	12	0	0
T41	0	11	0	0
T108	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	2586412	0	0
T4	198898	43099	0	0
T5	12788	0	0	0
T9	62586	0	0	0
T10	123012	0	0	0
T11	11727	0	0	0
T12	13617	0	0	0
T13	190561	31428	0	0
T26	17862	0	0	0
T29	16856	0	0	0
T41	0	24888	0	0
T51	14587	0	0	0
T75	0	1199	0	0
T99	0	46610	0	0
T101	0	1518	0	0
T103	0	9591	0	0
T105	0	9893	0	0
T106	0	23409	0	0
T176	0	8391	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	28772158	0	0
T1	26845	3412	0	0
T2	39407	24618	0	0
T3	12374	0	0	0
T4	198898	174529	0	0
T5	12788	0	0	0
T9	62586	0	0	0
T10	123012	0	0	0
T11	11727	0	0	0
T12	13617	0	0	0
T13	190561	157620	0	0
T41	0	137581	0	0
T42	0	54578	0	0
T99	0	139944	0	0
T100	0	30067	0	0
T102	0	31343	0	0
T114	0	3307	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T47,T119

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T10,T65,T74

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T84,T140
1	Covered	T84,T140

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T3,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T9
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Covered	T181,T184,T182
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T114,T115,T142
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T4,T13
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T5,T139,T164
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T76,T83,T84
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T4,T13
CheckFailError	317	Covered	T84,T140
FsmStateError	289	Covered	T1,T3,T9
MacroEccCorrError	221	Covered	T3,T10,T65
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T7,T77,T39
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T4,T13
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T84,T140
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T3,T9
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T3,T47,T119
MacroEccCorrError->NoError	235	Covered	T10,T65,T74
NoError->AccessError	256	Covered	T2,T4,T13
NoError->CheckFailError	317	Covered	T84,T140
NoError->FsmStateError	289	Covered	T1,T9,T10
NoError->MacroEccCorrError	221	Covered	T3,T10,T65

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T3,T47,T119
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T158,T160,T161
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T6,T8,T42
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T13
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T10,T65,T74
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T5,T139,T164
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T84,T140
1	0	Covered	T84,T140
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	474290662	473403068	0	0
DigestKnown_A	474290662	473403068	0	0
DigestOffsetMustBeRepresentable_A	1151	1151	0	0
EccErrorState_A	474290662	5544	0	0
ErrorKnown_A	474290662	473403068	0	0
FsmStateKnown_A	474290662	473403068	0	0
InitDoneKnown_A	474290662	473403068	0	0
InitReadLocksPartition_A	474290662	106550216	0	0
InitWriteLocksPartition_A	474290662	106550216	0	0
OffsetMustBeBlockAligned_A	1151	1151	0	0
OtpAddrKnown_A	474290662	473403068	0	0
OtpCmdKnown_A	474290662	473403068	0	0
OtpErrorState_A	474290662	40	0	0
OtpReqKnown_A	474290662	473403068	0	0
OtpSizeKnown_A	474290662	473403068	0	0
OtpWdataKnown_A	474290662	473403068	0	0
ReadLockPropagation_A	474290662	221635435	0	0
SizeMustBeBlockAligned_A	1151	1151	0	0
TlulGntKnown_A	474290662	473403068	0	0
TlulRdataKnown_A	474290662	473403068	0	0
TlulReadOnReadLock_A	474290662	8585	0	0
TlulRerrorKnown_A	474290662	473403068	0	0
TlulRvalidKnown_A	474290662	473403068	0	0
WriteLockPropagation_A	474290662	1763768	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	474290662	20770007	0	0
u_state_regs_A	474290662	473403068	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	5544	0	0
T72	12743	0	0	0
T73	16881	0	0	0
T84	14552	2666	0	0
T140	0	2878	0	0
T151	124408	0	0	0
T152	225937	0	0	0
T153	34164	0	0	0
T154	13793	0	0	0
T155	12000	0	0	0
T156	50435	0	0	0
T157	14571	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	106550216	0	0
T1	26845	17724	0	0
T2	39407	440	0	0
T3	12374	4467	0	0
T4	198898	1317	0	0
T5	12788	2289	0	0
T9	62586	55893	0	0
T10	123012	3925	0	0
T11	11727	618	0	0
T12	13617	3669	0	0
T13	190561	9685	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	106550216	0	0
T1	26845	17724	0	0
T2	39407	440	0	0
T3	12374	4467	0	0
T4	198898	1317	0	0
T5	12788	2289	0	0
T9	62586	55893	0	0
T10	123012	3925	0	0
T11	11727	618	0	0
T12	13617	3669	0	0
T13	190561	9685	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	40	0	0
T5	12788	1	0	0
T6	112716	0	0	0
T9	62586	0	0	0
T10	123012	0	0	0
T11	11727	0	0	0
T12	13617	0	0	0
T13	190561	0	0	0
T26	17862	0	0	0
T29	16856	0	0	0
T51	14587	0	0	0
T139	0	1	0	0
T158	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T166	0	1	0	0
T168	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	221635435	0	0
T2	39407	10350	0	0
T3	12374	0	0	0
T4	198898	93765	0	0
T5	12788	0	0	0
T6	0	797150	0	0
T7	0	458940	0	0
T8	0	349175	0	0
T9	62586	0	0	0
T10	123012	0	0	0
T11	11727	0	0	0
T12	13617	0	0	0
T13	190561	82238	0	0
T16	0	4546	0	0
T26	17862	0	0	0
T39	0	683811	0	0
T41	0	80869	0	0
T77	0	972488	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	8585	0	0
T1	26845	1	0	0
T2	39407	2	0	0
T3	12374	0	0	0
T4	198898	11	0	0
T5	12788	2	0	0
T6	0	76	0	0
T7	0	57	0	0
T9	62586	10	0	0
T10	123012	0	0	0
T11	11727	0	0	0
T12	13617	0	0	0
T13	190561	21	0	0
T29	0	1	0	0
T108	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	1763768	0	0
T4	198898	25238	0	0
T5	12788	0	0	0
T9	62586	0	0	0
T10	123012	0	0	0
T11	11727	0	0	0
T12	13617	0	0	0
T13	190561	0	0	0
T26	17862	0	0	0
T29	16856	0	0	0
T42	0	5746	0	0
T51	14587	0	0	0
T75	0	2965	0	0
T76	0	13398	0	0
T99	0	3257	0	0
T100	0	10623	0	0
T103	0	6205	0	0
T105	0	7388	0	0
T106	0	6819	0	0
T107	0	20015	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	20770007	0	0
T1	26845	3378	0	0
T2	39407	24567	0	0
T3	12374	0	0	0
T4	198898	174325	0	0
T5	12788	0	0	0
T9	62586	0	0	0
T10	123012	33979	0	0
T11	11727	0	0	0
T12	13617	0	0	0
T13	190561	0	0	0
T16	0	7678	0	0
T42	0	54391	0	0
T99	0	145602	0	0
T100	0	80739	0	0
T102	0	31241	0	0
T103	0	90612	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290662	473403068	0	0
T1	26845	26588	0	0
T2	39407	39046	0	0
T3	12374	12144	0	0
T4	198898	197523	0	0
T5	12788	12502	0	0
T9	62586	62353	0	0
T10	123012	122086	0	0
T11	11727	10914	0	0
T12	13617	13351	0	0
T13	190561	189751	0	0