Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_secded_inv_72_64_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 63.24 63.24
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 68.38 68.38
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 69.12 69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 69.12 69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 70.59 70.59
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 75.00 75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 76.47 76.47
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 77.21 77.21
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 80.88 80.88
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 85.29 85.29
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 88.24 88.24
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 97.14 97.14
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
63.24 63.24


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
63.24 63.24


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.38 68.38


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.38 68.38


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.59 70.59


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.59 70.59


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.21 77.21


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.21 77.21


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.88 80.88


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.88 80.88


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.29 85.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.29 85.29


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.24 88.24


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.24 88.24


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 97.14


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 97.14


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
data_o[63:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
syndrome_o[2:0] Yes Yes T83,T84,T140 Yes T83,T84,T140 OUTPUT
syndrome_o[7:3] No No No OUTPUT
err_o[0] Yes Yes *T83,*T84,*T140 Yes T83,T84,T140 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 172 63.24
Total Bits 0->1 136 86 63.24
Total Bits 1->0 136 86 63.24

Ports 2 0 0.00
Port Bits 272 172 63.24
Port Bits 0->1 136 86 63.24
Port Bits 1->0 136 86 63.24

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[3:0] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[5:4] No No No INPUT
data_i[6] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[7] No No No INPUT
data_i[8] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[9] No No No INPUT
data_i[13:10] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[14] No No No INPUT
data_i[17:15] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[19:18] No No No INPUT
data_i[21:20] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[22] No No No INPUT
data_i[23] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[26:24] No No No INPUT
data_i[28:27] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[30:29] No No No INPUT
data_i[32:31] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[33] No No No INPUT
data_i[35:34] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[38:36] No No No INPUT
data_i[39] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[40] No No No INPUT
data_i[49:41] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[50] No No No INPUT
data_i[52:51] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[56:53] No No No INPUT
data_i[58:57] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[60:59] No No No INPUT
data_i[71:61] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_o[3:0] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[5:4] No No No OUTPUT
data_o[6] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[7] No No No OUTPUT
data_o[8] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[9] No No No OUTPUT
data_o[13:10] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[14] No No No OUTPUT
data_o[17:15] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[19:18] No No No OUTPUT
data_o[21:20] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[22] No No No OUTPUT
data_o[23] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[26:24] No No No OUTPUT
data_o[28:27] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[30:29] No No No OUTPUT
data_o[32:31] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[33] No No No OUTPUT
data_o[35:34] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[38:36] No No No OUTPUT
data_o[39] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[40] No No No OUTPUT
data_o[49:41] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[50] No No No OUTPUT
data_o[52:51] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[56:53] No No No OUTPUT
data_o[58:57] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[60:59] No No No OUTPUT
data_o[63:61] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 186 68.38
Total Bits 0->1 136 93 68.38
Total Bits 1->0 136 93 68.38

Ports 2 0 0.00
Port Bits 272 186 68.38
Port Bits 0->1 136 93 68.38
Port Bits 1->0 136 93 68.38

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[1] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[3:2] No No No INPUT
data_i[4] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[5] No No No INPUT
data_i[6] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[7] No No No INPUT
data_i[10:8] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[11] No No No INPUT
data_i[14:12] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[16:15] No No No INPUT
data_i[23:17] Yes Yes *T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[24] No No No INPUT
data_i[25] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[27:26] No No No INPUT
data_i[33:28] Yes Yes *T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[35:34] No No No INPUT
data_i[36] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[37] No No No INPUT
data_i[40:38] Yes Yes *T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[41] No No No INPUT
data_i[45:42] Yes Yes *T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[46] No No No INPUT
data_i[48:47] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[49] No No No INPUT
data_i[51:50] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[53:52] No No No INPUT
data_i[59:54] Yes Yes T4,T10,T13 Yes T4,T10,T13 INPUT
data_i[60] No No No INPUT
data_i[62:61] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[63] No No No INPUT
data_i[67:64] Yes Yes *T4,*T10,*T13 Yes T4,T10,T13 INPUT
data_i[68] No No No INPUT
data_i[71:69] Yes Yes T4,T10,T13 Yes T4,T10,T13 INPUT
data_o[0] No No No OUTPUT
data_o[1] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[3:2] No No No OUTPUT
data_o[4] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[5] No No No OUTPUT
data_o[6] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[7] No No No OUTPUT
data_o[10:8] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[11] No No No OUTPUT
data_o[14:12] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[16:15] No No No OUTPUT
data_o[23:17] Yes Yes *T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[24] No No No OUTPUT
data_o[25] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[27:26] No No No OUTPUT
data_o[33:28] Yes Yes *T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[35:34] No No No OUTPUT
data_o[36] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[37] No No No OUTPUT
data_o[40:38] Yes Yes *T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[41] No No No OUTPUT
data_o[45:42] Yes Yes *T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[46] No No No OUTPUT
data_o[48:47] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[49] No No No OUTPUT
data_o[51:50] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[53:52] No No No OUTPUT
data_o[59:54] Yes Yes T4,T10,T13 Yes T4,T10,T13 OUTPUT
data_o[60] No No No OUTPUT
data_o[62:61] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 188 69.12
Total Bits 0->1 136 94 69.12
Total Bits 1->0 136 94 69.12

Ports 2 0 0.00
Port Bits 272 188 69.12
Port Bits 0->1 136 94 69.12
Port Bits 1->0 136 94 69.12

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[6:0] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[7] No No No INPUT
data_i[9:8] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[11:10] No No No INPUT
data_i[14:12] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[15] No No No INPUT
data_i[19:16] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[20] No No No INPUT
data_i[22:21] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[25:23] No No No INPUT
data_i[27:26] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[28] No No No INPUT
data_i[30:29] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[32:31] No No No INPUT
data_i[36:33] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[38:37] No No No INPUT
data_i[43:39] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[44] No No No INPUT
data_i[46:45] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[49:47] No No No INPUT
data_i[52:50] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[53] No No No INPUT
data_i[57:54] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[59:58] No No No INPUT
data_i[60] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[61] No No No INPUT
data_i[71:62] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_o[6:0] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[7] No No No OUTPUT
data_o[9:8] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[11:10] No No No OUTPUT
data_o[14:12] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[15] No No No OUTPUT
data_o[19:16] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[20] No No No OUTPUT
data_o[22:21] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[25:23] No No No OUTPUT
data_o[27:26] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[28] No No No OUTPUT
data_o[30:29] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[32:31] No No No OUTPUT
data_o[36:33] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[38:37] No No No OUTPUT
data_o[43:39] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[44] No No No OUTPUT
data_o[46:45] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[49:47] No No No OUTPUT
data_o[52:50] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[53] No No No OUTPUT
data_o[57:54] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[59:58] No No No OUTPUT
data_o[60] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[61] No No No OUTPUT
data_o[63:62] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 188 69.12
Total Bits 0->1 136 94 69.12
Total Bits 1->0 136 94 69.12

Ports 2 0 0.00
Port Bits 272 188 69.12
Port Bits 0->1 136 94 69.12
Port Bits 1->0 136 94 69.12

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[2] No No No INPUT
data_i[4:3] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[5] No No No INPUT
data_i[9:6] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[10] No No No INPUT
data_i[11] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[12] No No No INPUT
data_i[13] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[14] No No No INPUT
data_i[15] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[16] No No No INPUT
data_i[19:17] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[21:20] No No No INPUT
data_i[23:22] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[24] No No No INPUT
data_i[31:25] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[32] No No No INPUT
data_i[34:33] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[35] No No No INPUT
data_i[37:36] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[38] No No No INPUT
data_i[39] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[40] No No No INPUT
data_i[41] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[43:42] No No No INPUT
data_i[46:44] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[47] No No No INPUT
data_i[49:48] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[51:50] No No No INPUT
data_i[57:52] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[58] No No No INPUT
data_i[59] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[60] No No No INPUT
data_i[62:61] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[63] No No No INPUT
data_i[71:64] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_o[1:0] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[2] No No No OUTPUT
data_o[4:3] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[5] No No No OUTPUT
data_o[9:6] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[10] No No No OUTPUT
data_o[11] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[12] No No No OUTPUT
data_o[13] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[14] No No No OUTPUT
data_o[15] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[16] No No No OUTPUT
data_o[19:17] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[21:20] No No No OUTPUT
data_o[23:22] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[24] No No No OUTPUT
data_o[31:25] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[32] No No No OUTPUT
data_o[34:33] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[35] No No No OUTPUT
data_o[37:36] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[38] No No No OUTPUT
data_o[39] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[40] No No No OUTPUT
data_o[41] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[43:42] No No No OUTPUT
data_o[46:44] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[47] No No No OUTPUT
data_o[49:48] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[51:50] No No No OUTPUT
data_o[57:52] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[58] No No No OUTPUT
data_o[59] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[60] No No No OUTPUT
data_o[62:61] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 192 70.59
Total Bits 0->1 136 96 70.59
Total Bits 1->0 136 96 70.59

Ports 2 0 0.00
Port Bits 272 192 70.59
Port Bits 0->1 136 96 70.59
Port Bits 1->0 136 96 70.59

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[6:1] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[8:7] No No No INPUT
data_i[14:9] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[15] No No No INPUT
data_i[18:16] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[19] No No No INPUT
data_i[22:20] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[24:23] No No No INPUT
data_i[25] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[26] No No No INPUT
data_i[27] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[29:28] No No No INPUT
data_i[34:30] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[35] No No No INPUT
data_i[38:36] Yes Yes T4,T10,T13 Yes T4,T10,T13 INPUT
data_i[39] No No No INPUT
data_i[42:40] Yes Yes T4,T10,T13 Yes T4,T10,T13 INPUT
data_i[45:43] No No No INPUT
data_i[47:46] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[48] No No No INPUT
data_i[49] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[50] No No No INPUT
data_i[51] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[52] No No No INPUT
data_i[54:53] Yes Yes T4,T10,T13 Yes T4,T10,T13 INPUT
data_i[55] No No No INPUT
data_i[58:56] Yes Yes T4,T10,T13 Yes T4,T10,T13 INPUT
data_i[59] No No No INPUT
data_i[71:60] Yes Yes T4,T10,T13 Yes T4,T10,T13 INPUT
data_o[0] No No No OUTPUT
data_o[6:1] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[8:7] No No No OUTPUT
data_o[14:9] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[15] No No No OUTPUT
data_o[18:16] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[19] No No No OUTPUT
data_o[22:20] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[24:23] No No No OUTPUT
data_o[25] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[26] No No No OUTPUT
data_o[27] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[29:28] No No No OUTPUT
data_o[34:30] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[35] No No No OUTPUT
data_o[38:36] Yes Yes T4,T10,T13 Yes T4,T10,T13 OUTPUT
data_o[39] No No No OUTPUT
data_o[42:40] Yes Yes T4,T10,T13 Yes T4,T10,T13 OUTPUT
data_o[45:43] No No No OUTPUT
data_o[47:46] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[48] No No No OUTPUT
data_o[49] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[50] No No No OUTPUT
data_o[51] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[52] No No No OUTPUT
data_o[54:53] Yes Yes T4,T10,T13 Yes T4,T10,T13 OUTPUT
data_o[55] No No No OUTPUT
data_o[58:56] Yes Yes T4,T10,T13 Yes T4,T10,T13 OUTPUT
data_o[59] No No No OUTPUT
data_o[63:60] Yes Yes T4,T10,T13 Yes T4,T10,T13 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 204 75.00
Total Bits 0->1 136 102 75.00
Total Bits 1->0 136 102 75.00

Ports 2 0 0.00
Port Bits 272 204 75.00
Port Bits 0->1 136 102 75.00
Port Bits 1->0 136 102 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[4:0] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[5] No No No INPUT
data_i[7:6] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[8] No No No INPUT
data_i[10:9] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[11] No No No INPUT
data_i[13:12] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[14] No No No INPUT
data_i[15] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[17:16] No No No INPUT
data_i[18] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[19] No No No INPUT
data_i[23:20] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[24] No No No INPUT
data_i[25] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[26] No No No INPUT
data_i[37:27] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[38] No No No INPUT
data_i[44:39] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[47:45] No No No INPUT
data_i[51:48] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[52] No No No INPUT
data_i[55:53] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[56] No No No INPUT
data_i[59:57] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[61:60] No No No INPUT
data_i[71:62] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_o[4:0] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[5] No No No OUTPUT
data_o[7:6] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[8] No No No OUTPUT
data_o[10:9] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[11] No No No OUTPUT
data_o[13:12] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[14] No No No OUTPUT
data_o[15] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[17:16] No No No OUTPUT
data_o[18] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[19] No No No OUTPUT
data_o[23:20] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[24] No No No OUTPUT
data_o[25] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[26] No No No OUTPUT
data_o[37:27] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[38] No No No OUTPUT
data_o[44:39] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[47:45] No No No OUTPUT
data_o[51:48] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[52] No No No OUTPUT
data_o[55:53] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[56] No No No OUTPUT
data_o[59:57] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[61:60] No No No OUTPUT
data_o[63:62] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 208 76.47
Total Bits 0->1 136 104 76.47
Total Bits 1->0 136 104 76.47

Ports 2 0 0.00
Port Bits 272 208 76.47
Port Bits 0->1 136 104 76.47
Port Bits 1->0 136 104 76.47

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T4,T13,T41 Yes T4,T13,T41 INPUT
data_i[2] No No No INPUT
data_i[7:3] Yes Yes *T2,T4,*T10 Yes T2,T4,T10 INPUT
data_i[8] No No No INPUT
data_i[9] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[11:10] No No No INPUT
data_i[13:12] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[14] No No No INPUT
data_i[16:15] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[17] No No No INPUT
data_i[18] Yes Yes *T4,*T41,*T42 Yes T4,T41,T42 INPUT
data_i[19] No No No INPUT
data_i[28:20] Yes Yes *T2,T4,*T10 Yes T2,T4,T10 INPUT
data_i[30:29] No No No INPUT
data_i[36:31] Yes Yes T4,T41,T42 Yes T4,T41,T42 INPUT
data_i[37] No No No INPUT
data_i[45:38] Yes Yes T4,T13,T41 Yes T4,T13,T41 INPUT
data_i[48:46] No No No INPUT
data_i[53:49] Yes Yes T4,T13,T41 Yes T4,T13,T41 INPUT
data_i[54] No No No INPUT
data_i[56:55] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[57] No No No INPUT
data_i[60:58] Yes Yes *T2,T4,*T10 Yes T2,T4,T10 INPUT
data_i[61] No No No INPUT
data_i[71:62] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_o[1:0] Yes Yes T4,T13,T41 Yes T4,T13,T41 OUTPUT
data_o[2] No No No OUTPUT
data_o[7:3] Yes Yes *T2,T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[8] No No No OUTPUT
data_o[9] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[11:10] No No No OUTPUT
data_o[13:12] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[14] No No No OUTPUT
data_o[16:15] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[17] No No No OUTPUT
data_o[18] Yes Yes *T4,*T41,*T42 Yes T4,T41,T42 OUTPUT
data_o[19] No No No OUTPUT
data_o[28:20] Yes Yes *T2,T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[30:29] No No No OUTPUT
data_o[36:31] Yes Yes T4,T41,T42 Yes T4,T41,T42 OUTPUT
data_o[37] No No No OUTPUT
data_o[45:38] Yes Yes T4,T13,T41 Yes T4,T13,T41 OUTPUT
data_o[48:46] No No No OUTPUT
data_o[53:49] Yes Yes T4,T13,T41 Yes T4,T13,T41 OUTPUT
data_o[54] No No No OUTPUT
data_o[56:55] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[57] No No No OUTPUT
data_o[60:58] Yes Yes *T2,T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[61] No No No OUTPUT
data_o[63:62] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 210 77.21
Total Bits 0->1 136 105 77.21
Total Bits 1->0 136 105 77.21

Ports 2 0 0.00
Port Bits 272 210 77.21
Port Bits 0->1 136 105 77.21
Port Bits 1->0 136 105 77.21

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[1] No No No INPUT
data_i[4:2] Yes Yes *T2,T4,*T10 Yes T2,T4,T10 INPUT
data_i[5] No No No INPUT
data_i[12:6] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[13] No No No INPUT
data_i[17:14] Yes Yes T4,T13,T102 Yes T4,T13,T102 INPUT
data_i[18] No No No INPUT
data_i[21:19] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[24:22] No No No INPUT
data_i[28:25] Yes Yes T13,T102,*T101 Yes T13,T102,T99 INPUT
data_i[30:29] No No No INPUT
data_i[38:31] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[39] No No No INPUT
data_i[45:40] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[46] No No No INPUT
data_i[50:47] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[52:51] No No No INPUT
data_i[55:53] Yes Yes T13,T101,T65 Yes T13,T102,T99 INPUT
data_i[56] No No No INPUT
data_i[60:57] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[61] No No No INPUT
data_i[69:62] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[70] No No No INPUT
data_i[71] Yes Yes T13,T102,T99 Yes T13,T102,T101 INPUT
data_o[0] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[1] No No No OUTPUT
data_o[4:2] Yes Yes *T2,T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[5] No No No OUTPUT
data_o[12:6] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[13] No No No OUTPUT
data_o[17:14] Yes Yes T4,T13,T102 Yes T4,T13,T102 OUTPUT
data_o[18] No No No OUTPUT
data_o[21:19] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[24:22] No No No OUTPUT
data_o[28:25] Yes Yes T13,T102,*T101 Yes T13,T102,T99 OUTPUT
data_o[30:29] No No No OUTPUT
data_o[38:31] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[39] No No No OUTPUT
data_o[45:40] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[46] No No No OUTPUT
data_o[50:47] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[52:51] No No No OUTPUT
data_o[55:53] Yes Yes T13,T101,T65 Yes T13,T102,T99 OUTPUT
data_o[56] No No No OUTPUT
data_o[60:57] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[61] No No No OUTPUT
data_o[63:62] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 220 80.88
Total Bits 0->1 136 110 80.88
Total Bits 1->0 136 110 80.88

Ports 2 0 0.00
Port Bits 272 220 80.88
Port Bits 0->1 136 110 80.88
Port Bits 1->0 136 110 80.88

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] No No No INPUT
data_i[12:2] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[13] No No No INPUT
data_i[20:14] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[22:21] No No No INPUT
data_i[24:23] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[25] No No No INPUT
data_i[37:26] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[38] No No No INPUT
data_i[40:39] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[42:41] No No No INPUT
data_i[51:43] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[52] No No No INPUT
data_i[54:53] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[55] No No No INPUT
data_i[57:56] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[58] No No No INPUT
data_i[60:59] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[61] No No No INPUT
data_i[71:62] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_o[1:0] No No No OUTPUT
data_o[12:2] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[13] No No No OUTPUT
data_o[20:14] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[22:21] No No No OUTPUT
data_o[24:23] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[25] No No No OUTPUT
data_o[37:26] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[38] No No No OUTPUT
data_o[40:39] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[42:41] No No No OUTPUT
data_o[51:43] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[52] No No No OUTPUT
data_o[54:53] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[55] No No No OUTPUT
data_o[57:56] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[58] No No No OUTPUT
data_o[60:59] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[61] No No No OUTPUT
data_o[63:62] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 232 85.29
Total Bits 0->1 136 116 85.29
Total Bits 1->0 136 116 85.29

Ports 2 0 0.00
Port Bits 272 232 85.29
Port Bits 0->1 136 116 85.29
Port Bits 1->0 136 116 85.29

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[3:1] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[4] No No No INPUT
data_i[10:5] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[11] No No No INPUT
data_i[14:12] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[16:15] No No No INPUT
data_i[28:17] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[29] No No No INPUT
data_i[30] Yes Yes *T94 Yes T94 INPUT
data_i[32:31] No No No INPUT
data_i[46:33] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[47] No No No INPUT
data_i[61:48] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[62] No No No INPUT
data_i[71:63] Yes Yes T94,T2,T4 Yes T94,T2,T4 INPUT
data_o[0] No No No OUTPUT
data_o[3:1] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[4] No No No OUTPUT
data_o[10:5] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[11] No No No OUTPUT
data_o[14:12] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[16:15] No No No OUTPUT
data_o[28:17] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[29] No No No OUTPUT
data_o[30] Yes Yes *T94 Yes T94 OUTPUT
data_o[32:31] No No No OUTPUT
data_o[46:33] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[47] No No No OUTPUT
data_o[61:48] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[62] No No No OUTPUT
data_o[63] Yes Yes T94 Yes T94 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 240 88.24
Total Bits 0->1 136 120 88.24
Total Bits 1->0 136 120 88.24

Ports 2 0 0.00
Port Bits 272 240 88.24
Port Bits 0->1 136 120 88.24
Port Bits 1->0 136 120 88.24

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[9:0] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[10] No No No INPUT
data_i[12:11] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_i[13] No No No INPUT
data_i[15:14] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[16] No No No INPUT
data_i[18:17] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[20:19] No No No INPUT
data_i[34:21] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[35] No No No INPUT
data_i[47:36] Yes Yes *T92,*T2,*T4 Yes T92,T2,T4 INPUT
data_i[48] No No No INPUT
data_i[51:49] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 INPUT
data_i[52] No No No INPUT
data_i[71:53] Yes Yes T92,T2,T4 Yes T92,T2,T4 INPUT
data_o[9:0] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[10] No No No OUTPUT
data_o[12:11] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
data_o[13] No No No OUTPUT
data_o[15:14] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[16] No No No OUTPUT
data_o[18:17] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[20:19] No No No OUTPUT
data_o[34:21] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[35] No No No OUTPUT
data_o[47:36] Yes Yes *T92,*T2,*T4 Yes T92,T2,T4 OUTPUT
data_o[48] No No No OUTPUT
data_o[51:49] Yes Yes *T2,*T4,*T10 Yes T2,T4,T10 OUTPUT
data_o[52] No No No OUTPUT
data_o[63:53] Yes Yes T92,T2,T4 Yes T92,T2,T4 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 280 272 97.14
Total Bits 0->1 140 136 97.14
Total Bits 1->0 140 136 97.14

Ports 4 2 50.00
Port Bits 280 272 97.14
Port Bits 0->1 140 136 97.14
Port Bits 1->0 140 136 97.14

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_o[63:0] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
syndrome_o[2:0] No No No OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] No No No OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T13 Yes T1,T2,T13 INPUT
data_o[63:0] Yes Yes T1,T2,T13 Yes T1,T2,T13 OUTPUT
syndrome_o[2:0] Yes Yes T84,T138 Yes T84,T138 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T84,*T138 Yes T84,T138 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T102 Yes T1,T2,T102 INPUT
data_o[63:0] Yes Yes T1,T2,T102 Yes T1,T2,T102 OUTPUT
syndrome_o[2:0] Yes Yes T84,T140,T138 Yes T84,T140,T138 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T84,*T140,*T138 Yes T84,T140,T138 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T10,T99 Yes T4,T10,T99 INPUT
data_o[63:0] Yes Yes T4,T10,T99 Yes T4,T10,T99 OUTPUT
syndrome_o[2:0] Yes Yes T84,T140 Yes T84,T140 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T84,*T140 Yes T84,T140 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T101,T65,T109 Yes T101,T65,T109 INPUT
data_o[63:0] Yes Yes T101,T65,T109 Yes T101,T65,T109 OUTPUT
syndrome_o[2:0] Yes Yes T83,T84 Yes T83,T84 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T83,*T84 Yes T83,T84 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T27,T76,T53 Yes T27,T76,T53 INPUT
data_o[63:0] Yes Yes T27,T76,T53 Yes T27,T76,T53 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T97,T110,T111 Yes T97,T110,T111 INPUT
data_o[63:0] Yes Yes T97,T110,T111 Yes T97,T110,T111 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T42,T76 Yes T4,T42,T76 INPUT
data_o[63:0] Yes Yes T4,T42,T76 Yes T4,T42,T76 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T13,T76 Yes T4,T13,T98 INPUT
data_o[63:0] Yes Yes T4,T13,T76 Yes T4,T13,T98 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T76,T178,T181 Yes T99,T241,T76 INPUT
data_o[63:0] Yes Yes T76,T178,T181 Yes T99,T241,T76 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T26,T176,T124 Yes T26,T176,T124 INPUT
data_o[63:0] Yes Yes T26,T176,T124 Yes T26,T176,T124 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T110,T208,T76 Yes T110,T208,T76 INPUT
data_o[63:0] Yes Yes T110,T208,T76 Yes T110,T208,T76 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T76,T177,T124 Yes T76,T177,T124 INPUT
data_o[63:0] Yes Yes T76,T177,T124 Yes T76,T177,T124 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T4,T10 Yes T2,T4,T10 INPUT
data_o[63:0] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T26,T46 Yes T3,T26,T46 INPUT
data_o[63:0] Yes Yes T3,T26,T46 Yes T3,T26,T46 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T42,T97 Yes T4,T42,T97 INPUT
data_o[63:0] Yes Yes T4,T42,T97 Yes T4,T42,T97 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T10,T97 Yes T4,T10,T112 INPUT
data_o[63:0] Yes Yes T4,T10,T97 Yes T4,T10,T112 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T97,T103,T115 Yes T97,T98,T103 INPUT
data_o[63:0] Yes Yes T97,T103,T115 Yes T97,T98,T103 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T12,T54 Yes T2,T12,T54 INPUT
data_o[63:0] Yes Yes T2,T12,T54 Yes T2,T12,T54 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T42,T128,T105 Yes T42,T128,T105 INPUT
data_o[63:0] Yes Yes T42,T128,T105 Yes T42,T128,T105 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T13,T33,T110 Yes T13,T33,T110 INPUT
data_o[63:0] Yes Yes T13,T33,T110 Yes T13,T33,T110 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T13,T104 Yes T4,T13,T98 INPUT
data_o[63:0] Yes Yes T4,T13,T104 Yes T4,T13,T98 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T112,T27,T110 Yes T112,T27,T110 INPUT
data_o[63:0] Yes Yes T112,T27,T110 Yes T112,T27,T110 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T65,T75,T105 Yes T65,T75,T105 INPUT
data_o[63:0] Yes Yes T65,T75,T105 Yes T65,T75,T105 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T26,T41,T101 Yes T26,T41,T101 INPUT
data_o[63:0] Yes Yes T26,T41,T101 Yes T26,T41,T101 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T13,T99 Yes T4,T13,T99 INPUT
data_o[63:0] Yes Yes T4,T13,T99 Yes T4,T13,T99 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T99,T75 Yes T4,T99,T75 INPUT
data_o[63:0] Yes Yes T4,T99,T75 Yes T4,T99,T75 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T10,T12 Yes T2,T10,T12 INPUT
data_o[63:0] Yes Yes T2,T10,T12 Yes T2,T10,T12 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T33,T54,T27 Yes T33,T54,T98 INPUT
data_o[63:0] Yes Yes T33,T54,T27 Yes T33,T54,T98 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T41,T33 Yes T4,T41,T33 INPUT
data_o[63:0] Yes Yes T4,T41,T33 Yes T4,T41,T33 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T33,T97 Yes T4,T33,T97 INPUT
data_o[63:0] Yes Yes T4,T33,T97 Yes T4,T33,T97 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T26,T97 Yes T4,T26,T97 INPUT
data_o[63:0] Yes Yes T4,T26,T97 Yes T4,T26,T97 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T106,T76 Yes T2,T106,T76 INPUT
data_o[63:0] Yes Yes T2,T106,T76 Yes T2,T106,T76 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T105,T76,T124 Yes T105,T76,T124 INPUT
data_o[63:0] Yes Yes T105,T76,T124 Yes T105,T76,T124 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T42,T103 Yes T12,T42,T112 INPUT
data_o[63:0] Yes Yes T12,T42,T103 Yes T12,T42,T112 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T106,T76 Yes T4,T112,T106 INPUT
data_o[63:0] Yes Yes T4,T106,T76 Yes T4,T112,T106 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T41,T102,T75 Yes T41,T102,T75 INPUT
data_o[63:0] Yes Yes T41,T102,T75 Yes T41,T102,T75 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T75,T107,T124 Yes T112,T75,T107 INPUT
data_o[63:0] Yes Yes T75,T107,T124 Yes T112,T75,T107 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T10,T13,T16 Yes T10,T13,T16 INPUT
data_o[63:0] Yes Yes T10,T13,T16 Yes T10,T13,T16 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%