Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25982397

1

T1

1819

T2

385

T3

813

full_word

8525141

1

T1

752

T2

190

T3

628

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34507218	1			T1	2571		T2	575		T3	1441
auto[TlIntgErrCmd]	101	1			T254	1		T255	5		T256	4
auto[TlIntgErrData]	120	1			T254	7		T255	8		T256	3
auto[TlIntgErrBoth]	99	1			T254	2		T255	7		T256	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9948774

1

T1

1925

T2

342

T3

1244

auto[1]

24558764

1

T1

646

T2

233

T3

197

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6256252	1			T1	1437		T2	249		T3	708
auto[TlIntgErrNone]	partial	auto[1]	19725844	1			T1	382		T2	136		T3	105
auto[TlIntgErrNone]	full_word	auto[0]	3692368	1			T1	488		T2	93		T3	536
auto[TlIntgErrNone]	full_word	auto[1]	4832754	1			T1	264		T2	97		T3	92
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T254	1		T255	4		T256	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T255	1		T256	3		T265	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T332	1		T333	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T328	1		T334	1		-	-
auto[TlIntgErrData]	partial	auto[0]	59	1			T254	4		T255	4		T256	3
auto[TlIntgErrData]	partial	auto[1]	50	1			T254	2		T255	4		T265	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T332	1		T330	1		T327	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T254	1		T265	1		T326	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T254	2		T255	1		T256	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T255	6		T256	2		T265	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T329	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T329	1		T335	1		T331	1