Module Definition
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Module : otp_ctrl_lci
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_otp_ctrl_lci 100.00 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_ctrl_lci

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.23 94.16 96.15 97.22 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_count 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : otp_ctrl_lci
Line No.TotalCoveredPercent
TOTAL5252100.00
CONT_ASSIGN11411100.00
ALWAYS1174141100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26811100.00
ALWAYS27433100.00
ALWAYS27733100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
114 1 1
117 1 1
120 1 1
121 1 1
124 1 1
127 1 1
128 1 1
131 1 1
132 1 1
135 1 1
136 1 1
138 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
150 1 1
151 1 1
152 1 1
MISSING_ELSE
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
MISSING_ELSE
172 1 1
173 1 1
179 1 1
180 1 1
MISSING_ELSE
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
MISSING_ELSE
196 1 1
197 1 1
MISSING_ELSE
206 1 1
207 1 1
MISSING_ELSE
222 1 1
223 1 1
224 1 1
225 1 1
226 1 1
MISSING_ELSE
MISSING_ELSE
258 1 1
264 1 1
265 1 1
268 1 1
274 3 3
277 1 1
278 1 1
280 1 1


Cond Coverage for Module : otp_ctrl_lci
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       179
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT207,T220,T38

 LINE       185
 EXPRESSION (cnt == LastLcOtpWord)
            -----------1----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       190
 EXPRESSION (error_d != NoError)
            ----------1---------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT207,T220,T38

 LINE       206
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T22,T23

 LINE       225
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       265
 EXPRESSION (otp_req_o ? (64'(data[cnt])) : '0)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

FSM Coverage for Module : otp_ctrl_lci
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 9 9 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
ErrorSt 192 Covered T1,T2,T3
IdleSt 144 Covered T1,T2,T3
ResetSt 141 Covered T1,T2,T3
WriteSt 151 Covered T4,T5,T6
WriteWaitSt 164 Covered T4,T5,T6


transitionsLine No.CoveredTests
IdleSt->ErrorSt 223 Covered T1,T3,T4
IdleSt->WriteSt 151 Covered T4,T5,T6
ResetSt->ErrorSt 223 Covered T2,T11,T35
ResetSt->IdleSt 144 Covered T1,T2,T3
WriteSt->ErrorSt 223 Covered T312,T313,T314
WriteSt->WriteWaitSt 164 Covered T4,T5,T6
WriteWaitSt->ErrorSt 192 Covered T12,T37,T207
WriteWaitSt->IdleSt 186 Covered T4,T5,T6
WriteWaitSt->WriteSt 196 Covered T4,T5,T6



Branch Coverage for Module : otp_ctrl_lci
Line No.TotalCoveredPercent
Branches 24 24 100.00
TERNARY 265 2 2 100.00
CASE 138 15 15 100.00
IF 222 3 3 100.00
IF 274 2 2 100.00
IF 277 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 265 (otp_req_o) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 case (state_q) -2-: 143 if (lci_en_i) -3-: 150 if (lc_req_i) -4-: 163 if (otp_gnt_i) -5-: 173 if (otp_rvalid_i) -6-: 179 if ((otp_err_e'(otp_err_i) != NoError)) -7-: 185 if ((cnt == LastLcOtpWord)) -8-: 190 if ((error_d != NoError)) -9-: 206 if ((error_q == NoError))

Branches:
-1--2--3--4--5--6--7--8--9-StatusTests
ResetSt 1 - - - - - - - Covered T1,T2,T3
ResetSt 0 - - - - - - - Covered T1,T2,T3
IdleSt - 1 - - - - - - Covered T4,T5,T6
IdleSt - 0 - - - - - - Covered T1,T2,T3
WriteSt - - 1 - - - - - Covered T4,T5,T6
WriteSt - - 0 - - - - - Covered T4,T6,T12
WriteWaitSt - - - 1 1 - - - Covered T207,T220,T38
WriteWaitSt - - - 1 0 - - - Covered T4,T5,T6
WriteWaitSt - - - 1 - 1 1 - Covered T207,T220,T38
WriteWaitSt - - - 1 - 1 0 - Covered T4,T5,T6
WriteWaitSt - - - 1 - 0 - - Covered T4,T5,T6
WriteWaitSt - - - 0 - - - - Covered T4,T5,T6
ErrorSt - - - - - - - 1 Covered T21,T22,T23
ErrorSt - - - - - - - 0 Covered T1,T2,T3
default - - - - - - - - Covered T21,T22,T23


LineNo. Expression -1-: 222 if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err)) -2-: 225 if ((error_q == NoError))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 274 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 277 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : otp_ctrl_lci
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ErrorKnown_A 491744238 490863275 0 0
LcAckKnown_A 491744238 490863275 0 0
LcErrKnown_A 491744238 490863275 0 0
LcValueMustBeWiderThanNativeOtpWidth_A 1149 1149 0 0
LciIdleKnown_A 491744238 490863275 0 0
OtpAddrKnown_A 491744238 490863275 0 0
OtpCmdKnown_A 491744238 490863275 0 0
OtpReqKnown_A 491744238 490863275 0 0
OtpSizeKnown_A 491744238 490863275 0 0
OtpWdataKnown_A 491744238 490863275 0 0
u_state_regs_A 491744238 490863275 0 0


ErrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491744238 490863275 0 0
T1 12193 11933 0 0
T2 12872 12649 0 0
T3 9643 9446 0 0
T4 547929 547892 0 0
T5 19250 18779 0 0
T6 185555 185546 0 0
T7 10270 9438 0 0
T9 34294 34053 0 0
T10 9729 9540 0 0
T11 9794 9539 0 0

LcAckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491744238 490863275 0 0
T1 12193 11933 0 0
T2 12872 12649 0 0
T3 9643 9446 0 0
T4 547929 547892 0 0
T5 19250 18779 0 0
T6 185555 185546 0 0
T7 10270 9438 0 0
T9 34294 34053 0 0
T10 9729 9540 0 0
T11 9794 9539 0 0

LcErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491744238 490863275 0 0
T1 12193 11933 0 0
T2 12872 12649 0 0
T3 9643 9446 0 0
T4 547929 547892 0 0
T5 19250 18779 0 0
T6 185555 185546 0 0
T7 10270 9438 0 0
T9 34294 34053 0 0
T10 9729 9540 0 0
T11 9794 9539 0 0

LcValueMustBeWiderThanNativeOtpWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1149 1149 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

LciIdleKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491744238 490863275 0 0
T1 12193 11933 0 0
T2 12872 12649 0 0
T3 9643 9446 0 0
T4 547929 547892 0 0
T5 19250 18779 0 0
T6 185555 185546 0 0
T7 10270 9438 0 0
T9 34294 34053 0 0
T10 9729 9540 0 0
T11 9794 9539 0 0

OtpAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491744238 490863275 0 0
T1 12193 11933 0 0
T2 12872 12649 0 0
T3 9643 9446 0 0
T4 547929 547892 0 0
T5 19250 18779 0 0
T6 185555 185546 0 0
T7 10270 9438 0 0
T9 34294 34053 0 0
T10 9729 9540 0 0
T11 9794 9539 0 0

OtpCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491744238 490863275 0 0
T1 12193 11933 0 0
T2 12872 12649 0 0
T3 9643 9446 0 0
T4 547929 547892 0 0
T5 19250 18779 0 0
T6 185555 185546 0 0
T7 10270 9438 0 0
T9 34294 34053 0 0
T10 9729 9540 0 0
T11 9794 9539 0 0

OtpReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491744238 490863275 0 0
T1 12193 11933 0 0
T2 12872 12649 0 0
T3 9643 9446 0 0
T4 547929 547892 0 0
T5 19250 18779 0 0
T6 185555 185546 0 0
T7 10270 9438 0 0
T9 34294 34053 0 0
T10 9729 9540 0 0
T11 9794 9539 0 0

OtpSizeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491744238 490863275 0 0
T1 12193 11933 0 0
T2 12872 12649 0 0
T3 9643 9446 0 0
T4 547929 547892 0 0
T5 19250 18779 0 0
T6 185555 185546 0 0
T7 10270 9438 0 0
T9 34294 34053 0 0
T10 9729 9540 0 0
T11 9794 9539 0 0

OtpWdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491744238 490863275 0 0
T1 12193 11933 0 0
T2 12872 12649 0 0
T3 9643 9446 0 0
T4 547929 547892 0 0
T5 19250 18779 0 0
T6 185555 185546 0 0
T7 10270 9438 0 0
T9 34294 34053 0 0
T10 9729 9540 0 0
T11 9794 9539 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491744238 490863275 0 0
T1 12193 11933 0 0
T2 12872 12649 0 0
T3 9643 9446 0 0
T4 547929 547892 0 0
T5 19250 18779 0 0
T6 185555 185546 0 0
T7 10270 9438 0 0
T9 34294 34053 0 0
T10 9729 9540 0 0
T11 9794 9539 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%