Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.23	94.16	96.15	97.22		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	494730598	8349141	0	0
check_regwen_rd_A	494730598	2875	0	0
check_timeout_rd_A	494730598	2451	0	0
check_trigger_regwen_rd_A	494730598	2878	0	0
consistency_check_period_rd_A	494730598	2992	0	0
creator_sw_cfg_read_lock_rd_A	494730598	2562	0	0
direct_access_address_rd_A	494730598	1904	0	0
direct_access_wdata_0_rd_A	494730598	1357	0	0
direct_access_wdata_1_rd_A	494730598	1461	0	0
integrity_check_period_rd_A	494730598	2769	0	0
intr_enable_rd_A	494730598	3322	0	0
owner_sw_cfg_read_lock_rd_A	494730598	2232	0	0
rot_creator_auth_codesign_read_lock_rd_A	494730598	2582	0	0
rot_creator_auth_state_read_lock_rd_A	494730598	2531	0	0
vendor_test_read_lock_rd_A	494730598	2531	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	8349141	0	0
T4	547929	151709	0	0
T5	19250	0	0	0
T6	185555	39252	0	0
T8	516752	101525	0	0
T9	34294	0	0	0
T10	9729	0	0	0
T11	9794	0	0	0
T12	524799	0	0	0
T14	5369	0	0	0
T15	0	56598	0	0
T16	0	334460	0	0
T17	0	158156	0	0
T37	0	86966	0	0
T121	99665	0	0	0
T209	0	143152	0	0
T219	0	47076	0	0
T220	0	200091	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	2875	0	0
T8	516752	36	0	0
T12	524799	0	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T18	0	105	0	0
T19	0	62	0	0
T35	10165	0	0	0
T73	12914	0	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T145	0	101	0	0
T147	0	142	0	0
T186	0	117	0	0
T266	0	204	0	0
T268	0	34	0	0
T270	0	60	0	0
T315	0	46	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	2451	0	0
T8	516752	91	0	0
T12	524799	0	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T18	0	125	0	0
T19	0	43	0	0
T35	10165	0	0	0
T73	12914	0	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T145	0	110	0	0
T147	0	83	0	0
T186	0	100	0	0
T266	0	178	0	0
T268	0	52	0	0
T270	0	90	0	0
T315	0	46	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	2878	0	0
T8	516752	55	0	0
T12	524799	0	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T18	0	99	0	0
T19	0	65	0	0
T35	10165	0	0	0
T73	12914	0	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T145	0	77	0	0
T147	0	105	0	0
T186	0	82	0	0
T266	0	211	0	0
T268	0	20	0	0
T270	0	89	0	0
T315	0	43	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	2992	0	0
T8	516752	80	0	0
T12	524799	0	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T18	0	187	0	0
T19	0	49	0	0
T35	10165	0	0	0
T73	12914	0	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T145	0	63	0	0
T147	0	101	0	0
T186	0	130	0	0
T266	0	120	0	0
T268	0	45	0	0
T270	0	131	0	0
T315	0	55	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	2562	0	0
T8	516752	63	0	0
T12	524799	0	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T18	0	113	0	0
T19	0	31	0	0
T35	10165	0	0	0
T73	12914	0	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T145	0	96	0	0
T147	0	147	0	0
T186	0	97	0	0
T266	0	160	0	0
T268	0	35	0	0
T270	0	74	0	0
T315	0	19	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	1904	0	0
T8	516752	75	0	0
T12	524799	0	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T18	0	120	0	0
T19	0	54	0	0
T35	10165	0	0	0
T73	12914	0	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T145	0	81	0	0
T147	0	132	0	0
T186	0	107	0	0
T266	0	153	0	0
T268	0	28	0	0
T270	0	110	0	0
T315	0	40	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	1357	0	0
T8	516752	97	0	0
T12	524799	0	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T18	0	60	0	0
T19	0	35	0	0
T35	10165	0	0	0
T73	12914	0	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T145	0	46	0	0
T147	0	67	0	0
T186	0	56	0	0
T266	0	123	0	0
T268	0	36	0	0
T270	0	78	0	0
T315	0	22	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	1461	0	0
T8	516752	53	0	0
T12	524799	0	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T18	0	114	0	0
T19	0	25	0	0
T35	10165	0	0	0
T73	12914	0	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T145	0	64	0	0
T147	0	39	0	0
T186	0	45	0	0
T266	0	150	0	0
T268	0	63	0	0
T270	0	72	0	0
T315	0	12	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	2769	0	0
T8	516752	55	0	0
T12	524799	0	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T18	0	102	0	0
T19	0	49	0	0
T35	10165	0	0	0
T73	12914	0	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T145	0	98	0	0
T147	0	127	0	0
T186	0	62	0	0
T266	0	153	0	0
T268	0	45	0	0
T270	0	143	0	0
T315	0	41	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	3322	0	0
T8	516752	75	0	0
T12	524799	0	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T18	0	104	0	0
T19	0	34	0	0
T35	10165	0	0	0
T73	12914	0	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T145	0	75	0	0
T147	0	129	0	0
T184	0	2	0	0
T186	0	114	0	0
T266	0	141	0	0
T268	0	34	0	0
T270	0	139	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	2232	0	0
T8	516752	74	0	0
T12	524799	0	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T18	0	115	0	0
T19	0	57	0	0
T35	10165	0	0	0
T73	12914	0	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T145	0	44	0	0
T147	0	117	0	0
T186	0	83	0	0
T266	0	146	0	0
T268	0	17	0	0
T270	0	87	0	0
T315	0	16	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	2582	0	0
T8	516752	61	0	0
T12	524799	0	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T18	0	148	0	0
T19	0	56	0	0
T35	10165	0	0	0
T73	12914	0	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T145	0	75	0	0
T147	0	97	0	0
T186	0	88	0	0
T266	0	156	0	0
T268	0	31	0	0
T270	0	134	0	0
T315	0	53	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	2531	0	0
T8	516752	67	0	0
T12	524799	0	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T18	0	118	0	0
T19	0	55	0	0
T35	10165	0	0	0
T73	12914	0	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T145	0	122	0	0
T147	0	112	0	0
T186	0	65	0	0
T266	0	167	0	0
T268	0	38	0	0
T270	0	80	0	0
T315	0	36	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494730598	2531	0	0
T8	516752	77	0	0
T12	524799	0	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T18	0	100	0	0
T19	0	35	0	0
T35	10165	0	0	0
T73	12914	0	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T145	0	68	0	0
T147	0	150	0	0
T186	0	106	0	0
T266	0	136	0	0
T268	0	54	0	0
T270	0	84	0	0
T315	0	62	0	0