Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.23	94.16	96.15	97.22		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.23	94.16	96.15	97.22		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T73,T59,T167

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T168,T76,T164

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T85,T169,T170
1	Covered	T85,T169,T170

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T2,T4,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T12,T114

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T12,T114

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T4,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Covered	T103,T118,T172
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T119,T174,T173
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T4,T6
ReadSt->ReadWaitSt	252	Covered	T2,T4,T6
ReadWaitSt->ErrorSt	276	Covered	T114,T165,T198
ReadWaitSt->IdleSt	270	Covered	T2,T4,T6
ResetSt->ErrorSt	315	Covered	T83,T84,T85
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T4,T6
CheckFailError	317	Covered	T85,T169,T170
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T73,T168,T76
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T3,T4,T6
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T6,T8
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T85,T169,T170
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T73,T168,T164
MacroEccCorrError->NoError	235	Covered	T76,T80,T137
NoError->AccessError	256	Covered	T3,T4,T6
NoError->CheckFailError	317	Covered	T85,T169,T170
NoError->FsmStateError	289	Covered	T1,T2,T4
NoError->MacroEccCorrError	221	Covered	T73,T168,T76

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T114
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T73,T59,T167
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T174,T197,T221
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T4,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T12,T37,T27
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T4,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T168,T76,T164
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T4,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T114,T165,T198
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T85,T169,T170
1	0	Covered	T85,T169,T170
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	491744238	490863275	0	0
DigestKnown_A	491744238	490863275	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	491744238	16532	0	0
ErrorKnown_A	491744238	490863275	0	0
FsmStateKnown_A	491744238	490863275	0	0
InitDoneKnown_A	491744238	490863275	0	0
InitReadLocksPartition_A	491744238	107050750	0	0
InitWriteLocksPartition_A	491744238	107050750	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	491744238	490863275	0	0
OtpCmdKnown_A	491744238	490863275	0	0
OtpErrorState_A	491744238	37	0	0
OtpReqKnown_A	491744238	490863275	0	0
OtpSizeKnown_A	491744238	490863275	0	0
OtpWdataKnown_A	491744238	490863275	0	0
ReadLockPropagation_A	491744238	223570780	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	491744238	490863275	0	0
TlulRdataKnown_A	491744238	490863275	0	0
TlulReadOnReadLock_A	491744238	8290	0	0
TlulRerrorKnown_A	491744238	490863275	0	0
TlulRvalidKnown_A	491744238	490863275	0	0
WriteLockPropagation_A	491744238	3012938	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	491744238	35052401	0	0
u_state_regs_A	491744238	490863275	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	16532	0	0
T18	471454	0	0	0
T85	10919	3173	0	0
T140	10146	0	0	0
T169	0	3192	0	0
T170	0	3918	0	0
T176	0	3353	0	0
T177	0	2896	0	0
T186	806426	0	0	0
T187	55133	0	0	0
T188	779825	0	0	0
T189	4375	0	0	0
T190	127355	0	0	0
T191	10527	0	0	0
T192	23055	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	107050750	0	0
T1	12193	4797	0	0
T2	12872	3772	0	0
T3	9643	2964	0	0
T4	547929	461057	0	0
T5	19250	1961	0	0
T6	185555	569571	0	0
T7	10270	315	0	0
T9	34294	27270	0	0
T10	9729	3283	0	0
T11	9794	3660	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	107050750	0	0
T1	12193	4797	0	0
T2	12872	3772	0	0
T3	9643	2964	0	0
T4	547929	461057	0	0
T5	19250	1961	0	0
T6	185555	569571	0	0
T7	10270	315	0	0
T9	34294	27270	0	0
T10	9729	3283	0	0
T11	9794	3660	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	37	0	0
T13	21710	0	0	0
T27	62016	0	0	0
T37	400442	0	0	0
T44	31348	0	0	0
T72	85327	0	0	0
T73	12914	0	0	0
T75	29056	0	0	0
T101	14093	0	0	0
T102	124104	0	0	0
T114	96656	1	0	0
T165	0	1	0	0
T174	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0
T221	0	1	0	0
T222	0	1	0	0
T223	0	1	0	0
T224	0	1	0	0
T225	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	223570780	0	0
T3	9643	3485	0	0
T4	547929	463237	0	0
T5	19250	0	0	0
T6	185555	145753	0	0
T7	10270	2320	0	0
T8	0	139528	0	0
T9	34294	0	0	0
T10	9729	0	0	0
T11	9794	0	0	0
T12	0	470338	0	0
T14	5369	0	0	0
T16	0	654790	0	0
T37	0	191046	0	0
T112	0	34652	0	0
T114	0	4095	0	0
T121	99665	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	8290	0	0
T1	12193	10	0	0
T2	12872	0	0	0
T3	9643	1	0	0
T4	547929	23	0	0
T5	19250	1	0	0
T6	185555	20	0	0
T7	10270	0	0	0
T8	0	23	0	0
T9	34294	5	0	0
T10	9729	3	0	0
T11	9794	0	0	0
T12	0	71	0	0
T121	0	11	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	3012938	0	0
T12	524799	79518	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T27	0	2796	0	0
T28	0	10168	0	0
T35	10165	0	0	0
T44	31348	0	0	0
T73	12914	0	0	0
T104	0	6381	0	0
T105	0	83257	0	0
T108	0	2406	0	0
T109	0	2627	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	0	0	0
T115	0	1118	0	0
T137	0	4863	0	0
T165	0	7061	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	35052401	0	0
T1	12193	2818	0	0
T2	12872	0	0	0
T3	9643	0	0	0
T4	547929	0	0	0
T5	19250	0	0	0
T6	185555	0	0	0
T7	10270	0	0	0
T9	34294	0	0	0
T10	9729	0	0	0
T11	9794	0	0	0
T12	0	247496	0	0
T27	0	42592	0	0
T28	0	105919	0	0
T103	0	2988	0	0
T114	0	4132	0	0
T118	0	4554	0	0
T119	0	2768	0	0
T174	0	2309	0	0
T206	0	4129	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T73,T89,T139

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T114,T44,T164

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T83,T84,T85
1	Covered	T83,T84,T85

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T2,T4,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T11,T12

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T11,T12

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T4,T6
ReadWaitSt	252	Covered	T2,T4,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T4
IdleSt->ReadSt	236	Covered	T2,T4,T6
InitSt->ErrorSt	315	Covered	T103,T119,T118
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T2,T11,T174
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T6,T8
ReadSt->ReadWaitSt	252	Covered	T2,T4,T6
ReadWaitSt->ErrorSt	276	Covered	T114,T164,T226
ReadWaitSt->IdleSt	270	Covered	T2,T4,T6
ResetSt->ErrorSt	315	Covered	T83,T84,T85
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T6,T8
CheckFailError	317	Covered	T83,T84,T85
FsmStateError	289	Covered	T1,T3,T4
MacroEccCorrError	221	Covered	T114,T73,T44
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T6,T16
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T6,T8
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T83,T84,T85
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T3,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T73,T89,T139
MacroEccCorrError->NoError	235	Covered	T114,T44,T164
NoError->AccessError	256	Covered	T4,T6,T8
NoError->CheckFailError	317	Covered	T83,T84,T85
NoError->FsmStateError	289	Covered	T1,T3,T4
NoError->MacroEccCorrError	221	Covered	T114,T73,T44

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T73,T89,T139
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T227
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T4,T6
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T4,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T6,T27,T105
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T6,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T114,T44,T164
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T4,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T114,T164,T226
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T83,T84,T85
1	0	Covered	T83,T84,T85
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	491744238	490863275	0	0
DigestKnown_A	491744238	490863275	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	491744238	14595	0	0
ErrorKnown_A	491744238	490863275	0	0
FsmStateKnown_A	491744238	490863275	0	0
InitDoneKnown_A	491744238	490863275	0	0
InitReadLocksPartition_A	491744238	107234754	0	0
InitWriteLocksPartition_A	491744238	107234754	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	491744238	490863275	0	0
OtpCmdKnown_A	491744238	490863275	0	0
OtpErrorState_A	491744238	34	0	0
OtpReqKnown_A	491744238	490863275	0	0
OtpSizeKnown_A	491744238	490863275	0	0
OtpWdataKnown_A	491744238	490863275	0	0
ReadLockPropagation_A	491744238	222772227	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	491744238	490863275	0	0
TlulRdataKnown_A	491744238	490863275	0	0
TlulReadOnReadLock_A	491744238	7999	0	0
TlulRerrorKnown_A	491744238	490863275	0	0
TlulRvalidKnown_A	491744238	490863275	0	0
WriteLockPropagation_A	491744238	1653562	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	491744238	17246542	0	0
u_state_regs_A	491744238	490863275	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	14595	0	0
T51	16830	0	0	0
T56	13270	0	0	0
T83	14040	3608	0	0
T84	0	2539	0	0
T85	0	3173	0	0
T175	0	2379	0	0
T177	0	2896	0	0
T196	11817	0	0	0
T210	30516	0	0	0
T216	26870	0	0	0
T217	17598	0	0	0
T218	22644	0	0	0
T219	213932	0	0	0
T220	100713	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	107234754	0	0
T1	12193	4831	0	0
T2	12872	3813	0	0
T3	9643	3015	0	0
T4	547929	461069	0	0
T5	19250	2063	0	0
T6	185555	569673	0	0
T7	10270	366	0	0
T9	34294	27321	0	0
T10	9729	3334	0	0
T11	9794	3701	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	107234754	0	0
T1	12193	4831	0	0
T2	12872	3813	0	0
T3	9643	3015	0	0
T4	547929	461069	0	0
T5	19250	2063	0	0
T6	185555	569673	0	0
T7	10270	366	0	0
T9	34294	27321	0	0
T10	9729	3334	0	0
T11	9794	3701	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	34	0	0
T2	12872	1	0	0
T3	9643	0	0	0
T4	547929	0	0	0
T5	19250	0	0	0
T6	185555	0	0	0
T7	10270	0	0	0
T9	34294	0	0	0
T10	9729	0	0	0
T11	9794	1	0	0
T114	0	2	0	0
T121	99665	0	0	0
T164	0	2	0	0
T167	0	1	0	0
T226	0	1	0	0
T227	0	1	0	0
T228	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	222772227	0	0
T4	547929	463237	0	0
T5	19250	0	0	0
T6	185555	174233	0	0
T7	10270	2318	0	0
T8	516752	139281	0	0
T9	34294	0	0	0
T10	9729	0	0	0
T11	9794	0	0	0
T12	0	280589	0	0
T14	5369	0	0	0
T16	0	578779	0	0
T27	0	9078	0	0
T37	0	194640	0	0
T112	0	34631	0	0
T114	0	4135	0	0
T121	99665	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	7999	0	0
T1	12193	10	0	0
T2	12872	0	0	0
T3	9643	1	0	0
T4	547929	30	0	0
T5	19250	0	0	0
T6	185555	14	0	0
T7	10270	0	0	0
T8	0	30	0	0
T9	34294	6	0	0
T10	9729	0	0	0
T11	9794	0	0	0
T12	0	61	0	0
T111	0	14	0	0
T112	0	6	0	0
T121	0	14	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	1653562	0	0
T12	524799	25910	0	0
T15	173845	0	0	0
T16	133621	0	0	0
T28	0	10477	0	0
T35	10165	0	0	0
T44	31348	0	0	0
T73	12914	0	0	0
T105	0	65502	0	0
T106	0	5371	0	0
T109	0	4222	0	0
T110	0	12470	0	0
T111	86317	0	0	0
T112	43201	0	0	0
T113	9152	0	0	0
T114	96656	2050	0	0
T211	0	29932	0	0
T212	0	3138	0	0
T213	0	4244	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	17246542	0	0
T2	12872	2417	0	0
T3	9643	0	0	0
T4	547929	0	0	0
T5	19250	0	0	0
T6	185555	0	0	0
T7	10270	0	0	0
T9	34294	0	0	0
T10	9729	0	0	0
T11	9794	2546	0	0
T12	0	153754	0	0
T28	0	105681	0	0
T103	0	2954	0	0
T105	0	405411	0	0
T106	0	91566	0	0
T114	0	20174	0	0
T115	0	37741	0	0
T121	99665	0	0	0
T206	0	4095	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491744238	490863275	0	0
T1	12193	11933	0	0
T2	12872	12649	0	0
T3	9643	9446	0	0
T4	547929	547892	0	0
T5	19250	18779	0	0
T6	185555	185546	0	0
T7	10270	9438	0	0
T9	34294	34053	0	0
T10	9729	9540	0	0
T11	9794	9539	0	0