Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_secded_inv_72_64_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 63.24 63.24
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 68.38 68.38
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 69.12 69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 69.12 69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 69.85 69.85
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 75.00 75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 75.00 75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 76.47 76.47
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 76.47 76.47
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 76.47 76.47
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 79.41 79.41
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
63.24 63.24


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
63.24 63.24


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.38 68.38


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.38 68.38


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.12 69.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.85 69.85


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.85 69.85


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.41 79.41


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.41 79.41


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T3,T12,T114 Yes T1,T3,T12 INPUT
data_o[63:0] Yes Yes T3,T12,T114 Yes T1,T3,T12 OUTPUT
syndrome_o[2:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
syndrome_o[7:3] No No No OUTPUT
err_o[0] Yes Yes *T83,*T84,*T85 Yes T83,T84,T85 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 172 63.24
Total Bits 0->1 136 86 63.24
Total Bits 1->0 136 86 63.24

Ports 2 0 0.00
Port Bits 272 172 63.24
Port Bits 0->1 136 86 63.24
Port Bits 1->0 136 86 63.24

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[3:0] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[5:4] No No No INPUT
data_i[6] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[7] No No No INPUT
data_i[8] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[9] No No No INPUT
data_i[13:10] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[14] No No No INPUT
data_i[17:15] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[19:18] No No No INPUT
data_i[21:20] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[22] No No No INPUT
data_i[23] Yes Yes *T12,*T114,*T27 Yes T5,T12,T114 INPUT
data_i[26:24] No No No INPUT
data_i[28:27] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[30:29] No No No INPUT
data_i[32:31] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[33] No No No INPUT
data_i[35:34] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[38:36] No No No INPUT
data_i[39] Yes Yes *T12,*T114,*T27 Yes T5,T12,T114 INPUT
data_i[40] No No No INPUT
data_i[49:41] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[50] No No No INPUT
data_i[52:51] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[56:53] No No No INPUT
data_i[58:57] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[60:59] No No No INPUT
data_i[71:61] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_o[3:0] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[5:4] No No No OUTPUT
data_o[6] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[7] No No No OUTPUT
data_o[8] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[9] No No No OUTPUT
data_o[13:10] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[14] No No No OUTPUT
data_o[17:15] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[19:18] No No No OUTPUT
data_o[21:20] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[22] No No No OUTPUT
data_o[23] Yes Yes *T12,*T114,*T27 Yes T5,T12,T114 OUTPUT
data_o[26:24] No No No OUTPUT
data_o[28:27] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[30:29] No No No OUTPUT
data_o[32:31] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[33] No No No OUTPUT
data_o[35:34] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[38:36] No No No OUTPUT
data_o[39] Yes Yes *T12,*T114,*T27 Yes T5,T12,T114 OUTPUT
data_o[40] No No No OUTPUT
data_o[49:41] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[50] No No No OUTPUT
data_o[52:51] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[56:53] No No No OUTPUT
data_o[58:57] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[60:59] No No No OUTPUT
data_o[63:61] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 186 68.38
Total Bits 0->1 136 93 68.38
Total Bits 1->0 136 93 68.38

Ports 2 0 0.00
Port Bits 272 186 68.38
Port Bits 0->1 136 93 68.38
Port Bits 1->0 136 93 68.38

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[5:0] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[6] No No No INPUT
data_i[9:7] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[10] No No No INPUT
data_i[12:11] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[13] No No No INPUT
data_i[14] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[16:15] No No No INPUT
data_i[17] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[20:18] No No No INPUT
data_i[21] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[22] No No No INPUT
data_i[31:23] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[32] No No No INPUT
data_i[34:33] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[37:35] No No No INPUT
data_i[42:38] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[43] No No No INPUT
data_i[46:44] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[48:47] No No No INPUT
data_i[50:49] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[53:51] No No No INPUT
data_i[59:54] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[60] No No No INPUT
data_i[61] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[62] No No No INPUT
data_i[68:63] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[69] No No No INPUT
data_i[71:70] Yes Yes T12,T72,T106 Yes T12,T72,T106 INPUT
data_o[5:0] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[6] No No No OUTPUT
data_o[9:7] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[10] No No No OUTPUT
data_o[12:11] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[13] No No No OUTPUT
data_o[14] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[16:15] No No No OUTPUT
data_o[17] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[20:18] No No No OUTPUT
data_o[21] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[22] No No No OUTPUT
data_o[31:23] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[32] No No No OUTPUT
data_o[34:33] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[37:35] No No No OUTPUT
data_o[42:38] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[43] No No No OUTPUT
data_o[46:44] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[48:47] No No No OUTPUT
data_o[50:49] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[53:51] No No No OUTPUT
data_o[59:54] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[60] No No No OUTPUT
data_o[61] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[62] No No No OUTPUT
data_o[63] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 188 69.12
Total Bits 0->1 136 94 69.12
Total Bits 1->0 136 94 69.12

Ports 2 0 0.00
Port Bits 272 188 69.12
Port Bits 0->1 136 94 69.12
Port Bits 1->0 136 94 69.12

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[1] Yes Yes *T12,*T114,*T27 Yes T5,T12,T114 INPUT
data_i[3:2] No No No INPUT
data_i[4] Yes Yes *T12,*T114,*T27 Yes T5,T12,T114 INPUT
data_i[5] No No No INPUT
data_i[6] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[7] No No No INPUT
data_i[10:8] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[11] No No No INPUT
data_i[14:12] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[16:15] No No No INPUT
data_i[23:17] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[24] No No No INPUT
data_i[25] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[27:26] No No No INPUT
data_i[33:28] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[35:34] No No No INPUT
data_i[36] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[37] No No No INPUT
data_i[40:38] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[41] No No No INPUT
data_i[45:42] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[46] No No No INPUT
data_i[48:47] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[49] No No No INPUT
data_i[51:50] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[53:52] No No No INPUT
data_i[59:54] Yes Yes T12,T114,T72 Yes T12,T114,T72 INPUT
data_i[60] No No No INPUT
data_i[62:61] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[63] No No No INPUT
data_i[71:64] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_o[0] No No No OUTPUT
data_o[1] Yes Yes *T12,*T114,*T27 Yes T5,T12,T114 OUTPUT
data_o[3:2] No No No OUTPUT
data_o[4] Yes Yes *T12,*T114,*T27 Yes T5,T12,T114 OUTPUT
data_o[5] No No No OUTPUT
data_o[6] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[7] No No No OUTPUT
data_o[10:8] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[11] No No No OUTPUT
data_o[14:12] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[16:15] No No No OUTPUT
data_o[23:17] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[24] No No No OUTPUT
data_o[25] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[27:26] No No No OUTPUT
data_o[33:28] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[35:34] No No No OUTPUT
data_o[36] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[37] No No No OUTPUT
data_o[40:38] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[41] No No No OUTPUT
data_o[45:42] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[46] No No No OUTPUT
data_o[48:47] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[49] No No No OUTPUT
data_o[51:50] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[53:52] No No No OUTPUT
data_o[59:54] Yes Yes T12,T114,T72 Yes T12,T114,T72 OUTPUT
data_o[60] No No No OUTPUT
data_o[62:61] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 188 69.12
Total Bits 0->1 136 94 69.12
Total Bits 1->0 136 94 69.12

Ports 2 0 0.00
Port Bits 272 188 69.12
Port Bits 0->1 136 94 69.12
Port Bits 1->0 136 94 69.12

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[2] No No No INPUT
data_i[4:3] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[5] No No No INPUT
data_i[9:6] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[10] No No No INPUT
data_i[11] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[12] No No No INPUT
data_i[13] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[14] No No No INPUT
data_i[15] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[16] No No No INPUT
data_i[19:17] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[21:20] No No No INPUT
data_i[23:22] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[24] No No No INPUT
data_i[31:25] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[32] No No No INPUT
data_i[34:33] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[35] No No No INPUT
data_i[37:36] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[38] No No No INPUT
data_i[39] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[40] No No No INPUT
data_i[41] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[43:42] No No No INPUT
data_i[46:44] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[47] No No No INPUT
data_i[49:48] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[51:50] No No No INPUT
data_i[57:52] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[58] No No No INPUT
data_i[59] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[60] No No No INPUT
data_i[62:61] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[63] No No No INPUT
data_i[71:64] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_o[1:0] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[2] No No No OUTPUT
data_o[4:3] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[5] No No No OUTPUT
data_o[9:6] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[10] No No No OUTPUT
data_o[11] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[12] No No No OUTPUT
data_o[13] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[14] No No No OUTPUT
data_o[15] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[16] No No No OUTPUT
data_o[19:17] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[21:20] No No No OUTPUT
data_o[23:22] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[24] No No No OUTPUT
data_o[31:25] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[32] No No No OUTPUT
data_o[34:33] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[35] No No No OUTPUT
data_o[37:36] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[38] No No No OUTPUT
data_o[39] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[40] No No No OUTPUT
data_o[41] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[43:42] No No No OUTPUT
data_o[46:44] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[47] No No No OUTPUT
data_o[49:48] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[51:50] No No No OUTPUT
data_o[57:52] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[58] No No No OUTPUT
data_o[59] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[60] No No No OUTPUT
data_o[62:61] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 190 69.85
Total Bits 0->1 136 95 69.85
Total Bits 1->0 136 95 69.85

Ports 2 0 0.00
Port Bits 272 190 69.85
Port Bits 0->1 136 95 69.85
Port Bits 1->0 136 95 69.85

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[6:1] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[8:7] No No No INPUT
data_i[14:9] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[15] No No No INPUT
data_i[18:16] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[19] No No No INPUT
data_i[22:20] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[24:23] No No No INPUT
data_i[25] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[26] No No No INPUT
data_i[27] Yes Yes *T12,*T114,*T27 Yes T5,T12,T114 INPUT
data_i[29:28] No No No INPUT
data_i[34:30] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[35] No No No INPUT
data_i[38:36] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[39] No No No INPUT
data_i[42:40] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[45:43] No No No INPUT
data_i[47:46] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[48] No No No INPUT
data_i[49] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[50] No No No INPUT
data_i[51] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[52] No No No INPUT
data_i[54:53] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[55] No No No INPUT
data_i[58:56] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[59] No No No INPUT
data_i[64:60] Yes Yes T12,T114,*T27 Yes T5,T12,T114 INPUT
data_i[65] No No No INPUT
data_i[71:66] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_o[0] No No No OUTPUT
data_o[6:1] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[8:7] No No No OUTPUT
data_o[14:9] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[15] No No No OUTPUT
data_o[18:16] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[19] No No No OUTPUT
data_o[22:20] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[24:23] No No No OUTPUT
data_o[25] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[26] No No No OUTPUT
data_o[27] Yes Yes *T12,*T114,*T27 Yes T5,T12,T114 OUTPUT
data_o[29:28] No No No OUTPUT
data_o[34:30] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[35] No No No OUTPUT
data_o[38:36] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[39] No No No OUTPUT
data_o[42:40] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[45:43] No No No OUTPUT
data_o[47:46] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[48] No No No OUTPUT
data_o[49] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[50] No No No OUTPUT
data_o[51] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[52] No No No OUTPUT
data_o[54:53] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[55] No No No OUTPUT
data_o[58:56] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[59] No No No OUTPUT
data_o[63:60] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 204 75.00
Total Bits 0->1 136 102 75.00
Total Bits 1->0 136 102 75.00

Ports 2 0 0.00
Port Bits 272 204 75.00
Port Bits 0->1 136 102 75.00
Port Bits 1->0 136 102 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[6:0] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[7] No No No INPUT
data_i[9:8] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[11:10] No No No INPUT
data_i[14:12] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[15] No No No INPUT
data_i[19:16] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[20] No No No INPUT
data_i[22:21] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[25:23] No No No INPUT
data_i[27:26] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[28] No No No INPUT
data_i[30:29] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[32:31] No No No INPUT
data_i[36:33] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[38:37] No No No INPUT
data_i[43:39] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[44] No No No INPUT
data_i[46:45] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[49:47] No No No INPUT
data_i[71:50] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_o[6:0] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[7] No No No OUTPUT
data_o[9:8] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[11:10] No No No OUTPUT
data_o[14:12] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[15] No No No OUTPUT
data_o[19:16] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[20] No No No OUTPUT
data_o[22:21] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[25:23] No No No OUTPUT
data_o[27:26] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[28] No No No OUTPUT
data_o[30:29] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[32:31] No No No OUTPUT
data_o[36:33] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[38:37] No No No OUTPUT
data_o[43:39] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[44] No No No OUTPUT
data_o[46:45] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[49:47] No No No OUTPUT
data_o[63:50] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 204 75.00
Total Bits 0->1 136 102 75.00
Total Bits 1->0 136 102 75.00

Ports 2 0 0.00
Port Bits 272 204 75.00
Port Bits 0->1 136 102 75.00
Port Bits 1->0 136 102 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[4:0] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[5] No No No INPUT
data_i[7:6] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[8] No No No INPUT
data_i[10:9] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[11] No No No INPUT
data_i[13:12] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[14] No No No INPUT
data_i[15] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[17:16] No No No INPUT
data_i[18] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[19] No No No INPUT
data_i[23:20] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[24] No No No INPUT
data_i[25] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[26] No No No INPUT
data_i[37:27] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[38] No No No INPUT
data_i[44:39] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[47:45] No No No INPUT
data_i[51:48] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[52] No No No INPUT
data_i[55:53] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[56] No No No INPUT
data_i[59:57] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[61:60] No No No INPUT
data_i[71:62] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_o[4:0] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[5] No No No OUTPUT
data_o[7:6] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[8] No No No OUTPUT
data_o[10:9] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[11] No No No OUTPUT
data_o[13:12] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[14] No No No OUTPUT
data_o[15] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[17:16] No No No OUTPUT
data_o[18] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[19] No No No OUTPUT
data_o[23:20] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[24] No No No OUTPUT
data_o[25] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[26] No No No OUTPUT
data_o[37:27] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[38] No No No OUTPUT
data_o[44:39] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[47:45] No No No OUTPUT
data_o[51:48] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[52] No No No OUTPUT
data_o[55:53] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[56] No No No OUTPUT
data_o[59:57] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[61:60] No No No OUTPUT
data_o[63:62] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 208 76.47
Total Bits 0->1 136 104 76.47
Total Bits 1->0 136 104 76.47

Ports 2 0 0.00
Port Bits 272 208 76.47
Port Bits 0->1 136 104 76.47
Port Bits 1->0 136 104 76.47

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[3:1] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[4] No No No INPUT
data_i[8:5] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[9] No No No INPUT
data_i[10] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[11] No No No INPUT
data_i[14:12] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[16:15] No No No INPUT
data_i[27:17] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[32:28] No No No INPUT
data_i[41:33] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[42] No No No INPUT
data_i[51:43] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[52] No No No INPUT
data_i[54:53] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[55] No No No INPUT
data_i[61:56] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[63:62] No No No INPUT
data_i[71:64] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_o[0] No No No OUTPUT
data_o[3:1] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[4] No No No OUTPUT
data_o[8:5] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[9] No No No OUTPUT
data_o[10] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[11] No No No OUTPUT
data_o[14:12] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[16:15] No No No OUTPUT
data_o[27:17] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[32:28] No No No OUTPUT
data_o[41:33] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[42] No No No OUTPUT
data_o[51:43] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[52] No No No OUTPUT
data_o[54:53] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[55] No No No OUTPUT
data_o[61:56] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[63:62] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 208 76.47
Total Bits 0->1 136 104 76.47
Total Bits 1->0 136 104 76.47

Ports 2 0 0.00
Port Bits 272 208 76.47
Port Bits 0->1 136 104 76.47
Port Bits 1->0 136 104 76.47

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T12,T114,T72 Yes T12,T114,T72 INPUT
data_i[2] No No No INPUT
data_i[7:3] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[8] No No No INPUT
data_i[9] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[11:10] No No No INPUT
data_i[13:12] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[14] No No No INPUT
data_i[16:15] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[17] No No No INPUT
data_i[18] Yes Yes *T12,*T114,*T72 Yes T5,T12,T114 INPUT
data_i[19] No No No INPUT
data_i[28:20] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[30:29] No No No INPUT
data_i[36:31] Yes Yes T12,T114,T72 Yes T5,T12,T114 INPUT
data_i[37] No No No INPUT
data_i[45:38] Yes Yes T12,T114,T72 Yes T12,T114,T72 INPUT
data_i[48:46] No No No INPUT
data_i[53:49] Yes Yes T12,T114,T72 Yes T12,T114,T72 INPUT
data_i[54] No No No INPUT
data_i[56:55] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[57] No No No INPUT
data_i[60:58] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[61] No No No INPUT
data_i[71:62] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_o[1:0] Yes Yes T12,T114,T72 Yes T12,T114,T72 OUTPUT
data_o[2] No No No OUTPUT
data_o[7:3] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[8] No No No OUTPUT
data_o[9] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[11:10] No No No OUTPUT
data_o[13:12] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[14] No No No OUTPUT
data_o[16:15] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[17] No No No OUTPUT
data_o[18] Yes Yes *T12,*T114,*T72 Yes T5,T12,T114 OUTPUT
data_o[19] No No No OUTPUT
data_o[28:20] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[30:29] No No No OUTPUT
data_o[36:31] Yes Yes T12,T114,T72 Yes T5,T12,T114 OUTPUT
data_o[37] No No No OUTPUT
data_o[45:38] Yes Yes T12,T114,T72 Yes T12,T114,T72 OUTPUT
data_o[48:46] No No No OUTPUT
data_o[53:49] Yes Yes T12,T114,T72 Yes T12,T114,T72 OUTPUT
data_o[54] No No No OUTPUT
data_o[56:55] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[57] No No No OUTPUT
data_o[60:58] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[61] No No No OUTPUT
data_o[63:62] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 208 76.47
Total Bits 0->1 136 104 76.47
Total Bits 1->0 136 104 76.47

Ports 2 0 0.00
Port Bits 272 208 76.47
Port Bits 0->1 136 104 76.47
Port Bits 1->0 136 104 76.47

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[1] No No No INPUT
data_i[4:2] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[5] No No No INPUT
data_i[7:6] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[8] No No No INPUT
data_i[12:9] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[13] No No No INPUT
data_i[17:14] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[18] No No No INPUT
data_i[21:19] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[24:22] No No No INPUT
data_i[28:25] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[30:29] No No No INPUT
data_i[38:31] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[39] No No No INPUT
data_i[45:40] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[46] No No No INPUT
data_i[50:47] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[52:51] No No No INPUT
data_i[55:53] Yes Yes T12,T114,T27 Yes T12,T114,T27 INPUT
data_i[56] No No No INPUT
data_i[60:57] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[61] No No No INPUT
data_i[71:62] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_o[0] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[1] No No No OUTPUT
data_o[4:2] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[5] No No No OUTPUT
data_o[7:6] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[8] No No No OUTPUT
data_o[12:9] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[13] No No No OUTPUT
data_o[17:14] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[18] No No No OUTPUT
data_o[21:19] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[24:22] No No No OUTPUT
data_o[28:25] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[30:29] No No No OUTPUT
data_o[38:31] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[39] No No No OUTPUT
data_o[45:40] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[46] No No No OUTPUT
data_o[50:47] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[52:51] No No No OUTPUT
data_o[55:53] Yes Yes T12,T114,T27 Yes T12,T114,T27 OUTPUT
data_o[56] No No No OUTPUT
data_o[60:57] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[61] No No No OUTPUT
data_o[63:62] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 216 79.41
Total Bits 0->1 136 108 79.41
Total Bits 1->0 136 108 79.41

Ports 2 0 0.00
Port Bits 272 216 79.41
Port Bits 0->1 136 108 79.41
Port Bits 1->0 136 108 79.41

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] No No No INPUT
data_i[12:2] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[13] No No No INPUT
data_i[20:14] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 INPUT
data_i[22:21] No No No INPUT
data_i[24:23] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[25] No No No INPUT
data_i[36:26] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[38:37] No No No INPUT
data_i[40:39] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[42:41] No No No INPUT
data_i[51:43] Yes Yes *T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[52] No No No INPUT
data_i[54:53] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[55] No No No INPUT
data_i[57:56] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_i[58] No No No INPUT
data_i[60:59] Yes Yes T12,T114,T27 Yes T5,T12,T114 INPUT
data_i[61] No No No INPUT
data_i[71:62] Yes Yes T5,T12,T114 Yes T5,T12,T114 INPUT
data_o[1:0] No No No OUTPUT
data_o[12:2] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[13] No No No OUTPUT
data_o[20:14] Yes Yes *T5,*T12,*T114 Yes T5,T12,T114 OUTPUT
data_o[22:21] No No No OUTPUT
data_o[24:23] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[25] No No No OUTPUT
data_o[36:26] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[38:37] No No No OUTPUT
data_o[40:39] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[42:41] No No No OUTPUT
data_o[51:43] Yes Yes *T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[52] No No No OUTPUT
data_o[54:53] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[55] No No No OUTPUT
data_o[57:56] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
data_o[58] No No No OUTPUT
data_o[60:59] Yes Yes T12,T114,T27 Yes T5,T12,T114 OUTPUT
data_o[61] No No No OUTPUT
data_o[63:62] Yes Yes T5,T12,T114 Yes T5,T12,T114 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T12,T114 Yes T3,T12,T112 INPUT
data_o[63:0] Yes Yes T3,T12,T114 Yes T3,T12,T112 OUTPUT
syndrome_o[2:0] Yes Yes T85,T170,T171 Yes T85,T170,T171 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T85,*T170,*T171 Yes T85,T170,T171 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T12,T27 Yes T3,T12,T27 INPUT
data_o[63:0] Yes Yes T3,T12,T27 Yes T3,T12,T27 OUTPUT
syndrome_o[2:0] Yes Yes T84,T85,T170 Yes T84,T85,T170 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T84,*T85,*T170 Yes T84,T85,T170 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T114,T105 Yes T1,T12,T114 INPUT
data_o[63:0] Yes Yes T12,T114,T105 Yes T1,T12,T114 OUTPUT
syndrome_o[2:0] Yes Yes T83,T85,T170 Yes T83,T85,T170 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T83,*T85,*T170 Yes T83,T85,T170 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T27,T103 Yes T12,T27,T103 INPUT
data_o[63:0] Yes Yes T12,T27,T103 Yes T12,T27,T103 OUTPUT
syndrome_o[2:0] Yes Yes T85,T169,T170 Yes T85,T169,T170 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T85,*T169,*T170 Yes T85,T169,T170 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T114,T206 Yes T12,T114,T206 INPUT
data_o[63:0] Yes Yes T12,T114,T206 Yes T12,T114,T206 OUTPUT
syndrome_o[2:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T83,*T84,*T85 Yes T83,T84,T85 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T164,T105,T56 Yes T112,T164,T105 INPUT
data_o[63:0] Yes Yes T164,T105,T56 Yes T112,T164,T105 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T80,T210 Yes T12,T80,T210 INPUT
data_o[63:0] Yes Yes T12,T80,T210 Yes T12,T80,T210 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T106,T108,T226 Yes T106,T108,T226 INPUT
data_o[63:0] Yes Yes T106,T108,T226 Yes T106,T108,T226 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T105,T108 Yes T12,T105,T108 INPUT
data_o[63:0] Yes Yes T12,T105,T108 Yes T12,T105,T108 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T59,T106 Yes T12,T59,T106 INPUT
data_o[63:0] Yes Yes T12,T59,T106 Yes T12,T59,T106 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T117,T80,T137 Yes T117,T80,T137 INPUT
data_o[63:0] Yes Yes T117,T80,T137 Yes T117,T80,T137 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T103,T106,T56 Yes T103,T106,T56 INPUT
data_o[63:0] Yes Yes T103,T106,T56 Yes T103,T106,T56 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T107,T211 Yes T12,T107,T77 INPUT
data_o[63:0] Yes Yes T12,T107,T211 Yes T12,T107,T77 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T27,T105 Yes T12,T27,T103 INPUT
data_o[63:0] Yes Yes T12,T27,T105 Yes T12,T27,T103 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T35,T114 Yes T12,T35,T114 INPUT
data_o[63:0] Yes Yes T12,T35,T114 Yes T12,T35,T114 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T44,T72 Yes T12,T44,T72 INPUT
data_o[63:0] Yes Yes T12,T44,T72 Yes T12,T44,T72 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T12,T27 Yes T3,T12,T27 INPUT
data_o[63:0] Yes Yes T3,T12,T27 Yes T3,T12,T27 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T35,T113 Yes T12,T35,T113 INPUT
data_o[63:0] Yes Yes T12,T35,T113 Yes T12,T35,T113 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T3,T12,T35 Yes T3,T12,T35 INPUT
data_o[63:0] Yes Yes T3,T12,T35 Yes T3,T12,T35 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T112,T103 Yes T1,T12,T112 INPUT
data_o[63:0] Yes Yes T12,T112,T103 Yes T1,T12,T112 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T27,T103 Yes T12,T27,T103 INPUT
data_o[63:0] Yes Yes T12,T27,T103 Yes T12,T27,T103 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T27,T72 Yes T12,T27,T72 INPUT
data_o[63:0] Yes Yes T12,T27,T72 Yes T12,T27,T72 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T120,T106 Yes T12,T120,T106 INPUT
data_o[63:0] Yes Yes T12,T120,T106 Yes T12,T120,T106 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T27,T106,T154 Yes T27,T106,T154 INPUT
data_o[63:0] Yes Yes T27,T106,T154 Yes T27,T106,T154 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T35,T117 Yes T12,T35,T117 INPUT
data_o[63:0] Yes Yes T12,T35,T117 Yes T12,T35,T117 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T118,T115 Yes T12,T118,T115 INPUT
data_o[63:0] Yes Yes T12,T118,T115 Yes T12,T118,T115 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T206,T106 Yes T12,T206,T106 INPUT
data_o[63:0] Yes Yes T12,T206,T106 Yes T12,T206,T106 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T27,T168 Yes T12,T27,T168 INPUT
data_o[63:0] Yes Yes T12,T27,T168 Yes T12,T27,T168 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T5,T12,T105 Yes T5,T12,T105 INPUT
data_o[63:0] Yes Yes T5,T12,T105 Yes T5,T12,T105 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T105,T108 Yes T12,T105,T108 INPUT
data_o[63:0] Yes Yes T12,T105,T108 Yes T12,T105,T108 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T206,T28 Yes T12,T206,T28 INPUT
data_o[63:0] Yes Yes T12,T206,T28 Yes T12,T206,T28 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T105,T200 Yes T12,T105,T200 INPUT
data_o[63:0] Yes Yes T12,T105,T200 Yes T12,T105,T200 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T44,T72 Yes T12,T44,T72 INPUT
data_o[63:0] Yes Yes T12,T44,T72 Yes T12,T44,T72 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%