Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7142544	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7122189

1

T1

505

T2

886

T3

247

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8255118	1			T1	894		T2	2409		T3	1026
values[0x0]	2291216	1			T1	181		T2	155		T3	133
values[0x1]	3718399	1			T1	186		T2	131		T3	153

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4629087	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9635646

1

T1

688

T2

1372

T3

529

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49129	1			T1	2		T2	18		T3	5
valid_sources[0x01]	83104	1			T1	4		T2	5		T3	3
valid_sources[0x02]	55003	1			T1	8		T2	5		T8	9
valid_sources[0x03]	53816	1			T2	21		T8	7		T4	4
valid_sources[0x04]	52402	1			T1	1		T2	25		T8	12
valid_sources[0x05]	47960	1			T1	3		T2	10		T3	1
valid_sources[0x06]	57305	1			T2	10		T3	14		T8	5
valid_sources[0x07]	54415	1			T1	7		T2	9		T8	8
valid_sources[0x08]	48625	1			T1	1		T2	11		T3	3
valid_sources[0x09]	48779	1			T1	2		T2	16		T3	2
valid_sources[0x0a]	49718	1			T1	4		T2	7		T3	2
valid_sources[0x0b]	52852	1			T1	3		T2	12		T3	11
valid_sources[0x0c]	58072	1			T1	8		T2	6		T3	1
valid_sources[0x0d]	62998	1			T1	3		T2	15		T3	2
valid_sources[0x0e]	52761	1			T2	12		T3	4		T8	3
valid_sources[0x0f]	55317	1			T1	4		T2	20		T3	15
valid_sources[0x10]	48594	1			T1	12		T2	6		T3	4
valid_sources[0x11]	48871	1			T1	8		T2	7		T8	4
valid_sources[0x12]	51359	1			T1	4		T2	11		T3	4
valid_sources[0x13]	46883	1			T2	15		T3	10		T8	4
valid_sources[0x14]	54176	1			T1	3		T2	17		T3	5
valid_sources[0x15]	53491	1			T1	11		T2	32		T8	5
valid_sources[0x16]	58331	1			T1	5		T2	22		T3	10
valid_sources[0x17]	59170	1			T1	9		T2	13		T3	1
valid_sources[0x18]	52851	1			T1	13		T2	9		T8	7
valid_sources[0x19]	50774	1			T1	17		T2	13		T3	2
valid_sources[0x1a]	49384	1			T1	8		T2	6		T3	1
valid_sources[0x1b]	50173	1			T1	1		T2	2		T3	1
valid_sources[0x1c]	57327	1			T2	7		T3	9		T8	16
valid_sources[0x1d]	62774	1			T1	2		T2	9		T3	5
valid_sources[0x1e]	53512	1			T1	2		T2	10		T3	3
valid_sources[0x1f]	53862	1			T1	3		T2	7		T3	1
valid_sources[0x20]	50014	1			T1	14		T2	7		T8	10
valid_sources[0x21]	63813	1			T1	8		T2	3		T8	6
valid_sources[0x22]	48265	1			T1	1		T2	9		T3	4
valid_sources[0x23]	61799	1			T1	1		T2	6		T8	9
valid_sources[0x24]	46875	1			T1	9		T2	9		T3	3
valid_sources[0x25]	50799	1			T1	5		T2	11		T3	24
valid_sources[0x26]	55706	1			T2	11		T8	8		T4	3
valid_sources[0x27]	49196	1			T1	2		T2	13		T3	5
valid_sources[0x28]	58101	1			T1	9		T2	4		T8	7
valid_sources[0x29]	51132	1			T1	11		T2	11		T8	6
valid_sources[0x2a]	46961	1			T1	3		T2	10		T8	6
valid_sources[0x2b]	54279	1			T1	13		T2	11		T3	7
valid_sources[0x2c]	78826	1			T1	7		T2	14		T8	7
valid_sources[0x2d]	52558	1			T2	8		T8	11		T4	2
valid_sources[0x2e]	51239	1			T2	6		T8	8		T4	4
valid_sources[0x2f]	57490	1			T1	12		T2	4		T3	8
valid_sources[0x30]	65232	1			T2	9		T3	7		T8	6
valid_sources[0x31]	50937	1			T1	3		T2	2		T3	4
valid_sources[0x32]	47915	1			T1	2		T2	13		T3	2
valid_sources[0x33]	53061	1			T1	4		T2	13		T3	24
valid_sources[0x34]	55058	1			T1	16		T2	8		T3	7
valid_sources[0x35]	56027	1			T2	9		T3	2		T8	12
valid_sources[0x36]	53577	1			T1	9		T2	23		T3	4
valid_sources[0x37]	50157	1			T1	5		T2	15		T3	7
valid_sources[0x38]	52785	1			T1	13		T2	13		T3	27
valid_sources[0x39]	51995	1			T1	7		T2	8		T8	2
valid_sources[0x3a]	48883	1			T1	6		T2	9		T8	8
valid_sources[0x3b]	54092	1			T2	9		T3	1		T8	8
valid_sources[0x3c]	55368	1			T1	3		T2	11		T3	2
valid_sources[0x3d]	55968	1			T1	10		T2	14		T3	4
valid_sources[0x3e]	48918	1			T1	5		T2	7		T8	5
valid_sources[0x3f]	47633	1			T1	8		T2	11		T3	5
valid_sources[0x40]	63349	1			T1	13		T2	5		T3	3
valid_sources[0x41]	49240	1			T1	2		T2	11		T3	2
valid_sources[0x42]	49127	1			T2	14		T8	11		T4	3
valid_sources[0x43]	47766	1			T1	1		T2	8		T3	12
valid_sources[0x44]	50843	1			T1	2		T2	32		T3	3
valid_sources[0x45]	55189	1			T2	12		T3	5		T8	8
valid_sources[0x46]	48515	1			T1	3		T2	4		T3	8
valid_sources[0x47]	49912	1			T1	19		T2	5		T8	12
valid_sources[0x48]	49582	1			T1	12		T2	8		T8	8
valid_sources[0x49]	50275	1			T1	4		T2	12		T8	6
valid_sources[0x4a]	57503	1			T1	1		T2	4		T3	5
valid_sources[0x4b]	54304	1			T1	2		T2	11		T3	8
valid_sources[0x4c]	50898	1			T1	8		T2	9		T3	5
valid_sources[0x4d]	47541	1			T1	12		T2	10		T3	13
valid_sources[0x4e]	51023	1			T1	1		T2	15		T3	9
valid_sources[0x4f]	53724	1			T1	4		T2	8		T3	4
valid_sources[0x50]	153421	1			T1	1		T2	15		T8	8
valid_sources[0x51]	71034	1			T1	2		T2	7		T8	6
valid_sources[0x52]	61075	1			T1	1		T2	13		T3	4
valid_sources[0x53]	49703	1			T1	8		T2	11		T3	15
valid_sources[0x54]	48978	1			T1	4		T2	19		T8	10
valid_sources[0x55]	47714	1			T1	6		T2	12		T3	2
valid_sources[0x56]	46821	1			T1	8		T2	5		T3	7
valid_sources[0x57]	53234	1			T1	3		T2	5		T3	8
valid_sources[0x58]	57883	1			T1	10		T2	16		T8	5
valid_sources[0x59]	46100	1			T1	4		T2	10		T3	6
valid_sources[0x5a]	46898	1			T2	5		T3	8		T8	13
valid_sources[0x5b]	65416	1			T1	2		T2	13		T3	4
valid_sources[0x5c]	53325	1			T1	3		T2	12		T3	15
valid_sources[0x5d]	54174	1			T1	6		T2	13		T8	8
valid_sources[0x5e]	49177	1			T1	1		T2	17		T8	6
valid_sources[0x5f]	59790	1			T2	13		T3	2		T8	7
valid_sources[0x60]	49570	1			T1	7		T2	2		T8	5
valid_sources[0x61]	49484	1			T1	4		T2	5		T8	9
valid_sources[0x62]	53294	1			T2	4		T3	2		T8	5
valid_sources[0x63]	55344	1			T2	9		T8	10		T4	1
valid_sources[0x64]	62621	1			T1	4		T2	32		T3	15
valid_sources[0x65]	50565	1			T2	8		T3	13		T8	8
valid_sources[0x66]	47458	1			T1	2		T2	3		T3	6
valid_sources[0x67]	49100	1			T1	20		T2	12		T3	4
valid_sources[0x68]	53158	1			T1	3		T2	19		T3	1
valid_sources[0x69]	54381	1			T1	10		T2	9		T3	7
valid_sources[0x6a]	134308	1			T1	2		T2	6		T3	5
valid_sources[0x6b]	51697	1			T2	21		T3	13		T8	5
valid_sources[0x6c]	50811	1			T1	11		T2	21		T3	3
valid_sources[0x6d]	58255	1			T1	3		T2	9		T3	5
valid_sources[0x6e]	130315	1			T1	6		T2	26		T3	10
valid_sources[0x6f]	52046	1			T1	5		T2	7		T8	10
valid_sources[0x70]	82208	1			T2	6		T3	3		T8	7
valid_sources[0x71]	60208	1			T1	6		T2	3		T3	7
valid_sources[0x72]	58196	1			T1	6		T2	13		T3	1
valid_sources[0x73]	53158	1			T1	9		T2	10		T3	3
valid_sources[0x74]	49910	1			T1	7		T2	8		T3	21
valid_sources[0x75]	52873	1			T1	4		T2	19		T3	6
valid_sources[0x76]	50034	1			T1	2		T2	1		T3	8
valid_sources[0x77]	49335	1			T1	18		T2	10		T8	9
valid_sources[0x78]	56108	1			T1	1		T2	7		T3	5
valid_sources[0x79]	48671	1			T1	3		T2	13		T3	2
valid_sources[0x7a]	47922	1			T1	15		T2	15		T3	3
valid_sources[0x7b]	52052	1			T2	9		T3	16		T8	6
valid_sources[0x7c]	54369	1			T1	3		T2	10		T3	7
valid_sources[0x7d]	50294	1			T1	3		T2	6		T3	22
valid_sources[0x7e]	58469	1			T1	6		T2	11		T3	2
valid_sources[0x7f]	50662	1			T2	17		T8	9		T5	183
valid_sources[0x80]	49398	1			T1	2		T2	12		T3	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3395789

1

T1

358

T2

760

T3

137

values[0x0]

all_enables

biggest_size

1901362

1

T1

88

T2

78

T3

52

values[0x1]

all_enables

biggest_size

1825038

1

T1

59

T2

48

T3

58

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	242243	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8882260

1

T1

160

T2

40

T8

160

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2269404	1			T1	80		T2	20		T8	80
values[0x0]	3329749	1			T1	40		T2	10		T8	41
values[0x1]	3525350	1			T1	40		T2	10		T8	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	87351	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9037152

1

T1

160

T2

40

T8

160

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	36099	1			T5	7		T6	183		T11	504
valid_sources[0x01]	36264	1			T1	5		T5	6		T6	234
valid_sources[0x02]	35224	1			T1	3		T6	311		T11	470
valid_sources[0x03]	35867	1			T8	2		T5	6		T6	331
valid_sources[0x04]	35264	1			T5	6		T6	283		T110	2
valid_sources[0x05]	35345	1			T1	2		T5	14		T6	288
valid_sources[0x06]	35389	1			T8	1		T5	7		T6	204
valid_sources[0x07]	35278	1			T5	3		T6	173		T109	1
valid_sources[0x08]	36273	1			T1	2		T5	3		T6	221
valid_sources[0x09]	36110	1			T8	1		T5	13		T6	286
valid_sources[0x0a]	37503	1			T4	1		T5	4		T6	259
valid_sources[0x0b]	36069	1			T1	2		T8	1		T6	288
valid_sources[0x0c]	35935	1			T1	7		T5	2		T6	283
valid_sources[0x0d]	37682	1			T5	2		T6	272		T11	501
valid_sources[0x0e]	36319	1			T1	2		T5	10		T6	528
valid_sources[0x0f]	35867	1			T5	5		T6	263		T7	2
valid_sources[0x10]	34582	1			T2	14		T5	1		T6	213
valid_sources[0x11]	35883	1			T1	3		T8	2		T5	4
valid_sources[0x12]	36399	1			T1	1		T8	2		T5	5
valid_sources[0x13]	36802	1			T1	1		T8	1		T5	10
valid_sources[0x14]	34074	1			T2	13		T5	2		T6	275
valid_sources[0x15]	35801	1			T1	2		T8	2		T5	1
valid_sources[0x16]	36205	1			T8	2		T5	1		T6	195
valid_sources[0x17]	35613	1			T5	8		T6	342		T109	6
valid_sources[0x18]	36660	1			T5	3		T6	247		T11	491
valid_sources[0x19]	34715	1			T1	1		T5	5		T6	329
valid_sources[0x1a]	35742	1			T5	6		T6	280		T11	509
valid_sources[0x1b]	35264	1			T8	1		T4	2		T5	7
valid_sources[0x1c]	35309	1			T1	1		T5	1		T6	180
valid_sources[0x1d]	35751	1			T1	1		T5	8		T6	252
valid_sources[0x1e]	35245	1			T5	1		T6	219		T110	1
valid_sources[0x1f]	35823	1			T1	1		T5	3		T6	473
valid_sources[0x20]	35548	1			T8	1		T5	3		T6	175
valid_sources[0x21]	35643	1			T1	1		T5	9		T6	295
valid_sources[0x22]	34588	1			T8	1		T5	6		T6	432
valid_sources[0x23]	36199	1			T1	1		T5	5		T6	303
valid_sources[0x24]	36549	1			T5	4		T6	319		T110	6
valid_sources[0x25]	36960	1			T1	1		T5	3		T6	257
valid_sources[0x26]	34295	1			T5	4		T6	218		T11	415
valid_sources[0x27]	35379	1			T5	5		T6	309		T11	456
valid_sources[0x28]	35481	1			T1	1		T5	10		T6	339
valid_sources[0x29]	35012	1			T5	8		T6	129		T11	443
valid_sources[0x2a]	36987	1			T1	2		T8	1		T5	3
valid_sources[0x2b]	34550	1			T5	9		T6	338		T110	1
valid_sources[0x2c]	37094	1			T1	4		T5	15		T6	444
valid_sources[0x2d]	34824	1			T5	9		T6	125		T11	477
valid_sources[0x2e]	35632	1			T1	1		T6	319		T110	1
valid_sources[0x2f]	37088	1			T5	5		T6	305		T11	526
valid_sources[0x30]	35985	1			T1	1		T8	4		T5	6
valid_sources[0x31]	35796	1			T1	1		T8	1		T5	7
valid_sources[0x32]	35114	1			T5	5		T6	213		T11	469
valid_sources[0x33]	37236	1			T8	2		T5	4		T6	199
valid_sources[0x34]	34462	1			T5	4		T6	294		T11	518
valid_sources[0x35]	36202	1			T1	1		T5	6		T6	387
valid_sources[0x36]	34871	1			T5	4		T6	528		T27	6
valid_sources[0x37]	34247	1			T5	4		T6	257		T11	470
valid_sources[0x38]	34272	1			T8	2		T6	207		T27	2
valid_sources[0x39]	35824	1			T1	1		T5	6		T6	394
valid_sources[0x3a]	34353	1			T8	1		T5	3		T6	320
valid_sources[0x3b]	35416	1			T1	2		T5	5		T6	208
valid_sources[0x3c]	36260	1			T1	2		T8	4		T5	4
valid_sources[0x3d]	35627	1			T1	1		T8	1		T5	8
valid_sources[0x3e]	34667	1			T8	2		T5	8		T6	325
valid_sources[0x3f]	37984	1			T8	3		T5	2		T6	262
valid_sources[0x40]	35465	1			T1	2		T5	1		T6	399
valid_sources[0x41]	35321	1			T4	1		T5	7		T6	377
valid_sources[0x42]	36656	1			T5	7		T6	367		T27	2
valid_sources[0x43]	35064	1			T1	1		T5	2		T6	294
valid_sources[0x44]	36104	1			T8	1		T5	2		T6	329
valid_sources[0x45]	35735	1			T1	4		T5	4		T6	380
valid_sources[0x46]	37015	1			T5	6		T6	383		T11	506
valid_sources[0x47]	35844	1			T8	1		T5	10		T6	236
valid_sources[0x48]	35767	1			T8	4		T5	7		T6	226
valid_sources[0x49]	36017	1			T5	7		T6	259		T11	520
valid_sources[0x4a]	35670	1			T8	3		T4	2		T5	3
valid_sources[0x4b]	34802	1			T8	1		T5	6		T6	284
valid_sources[0x4c]	35727	1			T1	1		T5	2		T6	162
valid_sources[0x4d]	34168	1			T5	8		T6	226		T11	439
valid_sources[0x4e]	36612	1			T5	12		T6	222		T11	453
valid_sources[0x4f]	35445	1			T5	4		T6	270		T7	1
valid_sources[0x50]	35077	1			T1	3		T2	3		T4	1
valid_sources[0x51]	35143	1			T1	5		T5	8		T6	136
valid_sources[0x52]	36213	1			T5	4		T6	255		T11	463
valid_sources[0x53]	34829	1			T5	10		T6	239		T110	1
valid_sources[0x54]	36034	1			T8	1		T5	9		T6	189
valid_sources[0x55]	37548	1			T8	6		T5	5		T6	317
valid_sources[0x56]	35096	1			T5	3		T6	256		T11	513
valid_sources[0x57]	36010	1			T5	4		T6	101		T11	448
valid_sources[0x58]	34778	1			T8	1		T4	1		T5	1
valid_sources[0x59]	36130	1			T1	2		T2	10		T5	4
valid_sources[0x5a]	34483	1			T1	1		T8	1		T5	4
valid_sources[0x5b]	35199	1			T8	1		T5	4		T6	256
valid_sources[0x5c]	35033	1			T8	1		T5	4		T6	245
valid_sources[0x5d]	35666	1			T5	6		T6	371		T27	6
valid_sources[0x5e]	35726	1			T5	9		T6	430		T11	495
valid_sources[0x5f]	35462	1			T5	4		T6	170		T11	510
valid_sources[0x60]	35596	1			T8	1		T6	231		T11	473
valid_sources[0x61]	35449	1			T8	2		T4	1		T5	3
valid_sources[0x62]	36558	1			T1	1		T5	6		T6	259
valid_sources[0x63]	35599	1			T5	7		T6	312		T27	8
valid_sources[0x64]	34754	1			T4	1		T5	1		T6	206
valid_sources[0x65]	35675	1			T8	2		T4	1		T5	6
valid_sources[0x66]	36345	1			T1	2		T4	1		T5	4
valid_sources[0x67]	34862	1			T8	1		T5	1		T6	228
valid_sources[0x68]	35969	1			T1	2		T5	2		T6	259
valid_sources[0x69]	34818	1			T8	1		T5	3		T6	328
valid_sources[0x6a]	35422	1			T8	1		T5	6		T6	186
valid_sources[0x6b]	35357	1			T5	5		T6	354		T11	460
valid_sources[0x6c]	35821	1			T1	3		T5	11		T6	300
valid_sources[0x6d]	36050	1			T5	10		T6	271		T11	433
valid_sources[0x6e]	35629	1			T1	2		T8	1		T5	2
valid_sources[0x6f]	36370	1			T5	6		T6	296		T109	3
valid_sources[0x70]	34515	1			T5	1		T6	330		T11	464
valid_sources[0x71]	34949	1			T8	2		T5	4		T6	228
valid_sources[0x72]	36054	1			T5	2		T6	145		T7	1
valid_sources[0x73]	34409	1			T5	6		T6	190		T110	1
valid_sources[0x74]	36251	1			T1	2		T8	3		T5	9
valid_sources[0x75]	35876	1			T8	4		T5	5		T6	259
valid_sources[0x76]	35027	1			T5	2		T6	307		T11	521
valid_sources[0x77]	37050	1			T1	1		T5	3		T6	396
valid_sources[0x78]	35273	1			T4	2		T5	2		T6	497
valid_sources[0x79]	36009	1			T5	8		T6	241		T27	2
valid_sources[0x7a]	35695	1			T8	5		T5	2		T6	407
valid_sources[0x7b]	36398	1			T1	1		T5	2		T6	366
valid_sources[0x7c]	36224	1			T8	1		T5	4		T6	214
valid_sources[0x7d]	35299	1			T8	1		T5	4		T6	267
valid_sources[0x7e]	35784	1			T1	1		T5	1		T6	245
valid_sources[0x7f]	35081	1			T8	1		T5	4		T6	243
valid_sources[0x80]	36311	1			T5	6		T6	310		T11	507

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2255991

1

T1

80

T2

20

T8

80

values[0x0]

all_enables

biggest_size

3313290

1

T1

40

T2

10

T8

41

values[0x1]

all_enables

biggest_size

3312979

1

T1

40

T2

10

T8

39