Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24907038

1

T1

756

T2

1809

T3

1065

full_word

8197046

1

T1

505

T2

886

T3

247

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33103754	1			T1	1261		T2	2695		T3	1312
auto[TlIntgErrCmd]	106	1			T265	6		T266	5		T267	6
auto[TlIntgErrData]	103	1			T265	9		T266	6		T267	10
auto[TlIntgErrBoth]	121	1			T265	5		T266	9		T267	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9556933

1

T1

894

T2

2409

T3

1026

auto[1]

23547151

1

T1

367

T2

286

T3

286

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6028950	1			T1	536		T2	1649		T3	889
auto[TlIntgErrNone]	partial	auto[1]	18877781	1			T1	220		T2	160		T3	176
auto[TlIntgErrNone]	full_word	auto[0]	3527833	1			T1	358		T2	760		T3	137
auto[TlIntgErrNone]	full_word	auto[1]	4669190	1			T1	147		T2	126		T3	110
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T265	4		T266	2		T275	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T265	2		T266	2		T267	6
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T349	1		T350	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T266	1		T351	1		T349	2
auto[TlIntgErrData]	partial	auto[0]	50	1			T265	5		T266	3		T267	4
auto[TlIntgErrData]	partial	auto[1]	42	1			T265	3		T266	3		T267	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T265	1		T267	1		T351	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T267	1		T347	1		T352	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T265	2		T266	5		T267	3
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T265	3		T266	4		T267	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T273	2		T351	1		T353	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T354	1		T352	1		-	-