Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	94.16	96.15	96.83		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	452088886	8010693	0	0
check_regwen_rd_A	452088886	3967	0	0
check_timeout_rd_A	452088886	3021	0	0
check_trigger_regwen_rd_A	452088886	4333	0	0
consistency_check_period_rd_A	452088886	4282	0	0
creator_sw_cfg_read_lock_rd_A	452088886	3030	0	0
direct_access_address_rd_A	452088886	2070	0	0
direct_access_wdata_0_rd_A	452088886	1367	0	0
direct_access_wdata_1_rd_A	452088886	1691	0	0
integrity_check_period_rd_A	452088886	4244	0	0
intr_enable_rd_A	452088886	5388	0	0
owner_sw_cfg_read_lock_rd_A	452088886	2929	0	0
rot_creator_auth_codesign_read_lock_rd_A	452088886	2856	0	0
rot_creator_auth_state_read_lock_rd_A	452088886	2892	0	0
vendor_test_read_lock_rd_A	452088886	2822	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	8010693	0	0
T6	676357	67135	0	0
T7	97039	0	0	0
T10	13504	0	0	0
T11	531918	104039	0	0
T12	0	85554	0	0
T14	0	40794	0	0
T26	0	125830	0	0
T27	97822	0	0	0
T28	109865	0	0	0
T36	0	263223	0	0
T37	0	30532	0	0
T51	24475	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T251	0	170761	0	0
T276	0	49501	0	0
T277	0	106015	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	3967	0	0
T6	676357	38	0	0
T7	97039	0	0	0
T10	13504	0	0	0
T11	531918	99	0	0
T14	0	60	0	0
T27	97822	0	0	0
T28	109865	0	0	0
T51	24475	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T288	0	53	0	0
T289	0	103	0	0
T329	0	23	0	0
T330	0	54	0	0
T331	0	102	0	0
T332	0	126	0	0
T333	0	121	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	3021	0	0
T6	676357	95	0	0
T7	97039	0	0	0
T10	13504	0	0	0
T11	531918	162	0	0
T14	0	73	0	0
T27	97822	0	0	0
T28	109865	0	0	0
T51	24475	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T288	0	33	0	0
T289	0	121	0	0
T329	0	47	0	0
T330	0	64	0	0
T331	0	83	0	0
T332	0	98	0	0
T333	0	120	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	4333	0	0
T6	676357	31	0	0
T7	97039	0	0	0
T10	13504	0	0	0
T11	531918	154	0	0
T14	0	69	0	0
T27	97822	0	0	0
T28	109865	0	0	0
T51	24475	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T288	0	55	0	0
T289	0	104	0	0
T329	0	24	0	0
T330	0	20	0	0
T331	0	116	0	0
T332	0	106	0	0
T333	0	152	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	4282	0	0
T6	676357	32	0	0
T7	97039	0	0	0
T10	13504	0	0	0
T11	531918	92	0	0
T14	0	52	0	0
T27	97822	0	0	0
T28	109865	0	0	0
T51	24475	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T288	0	58	0	0
T289	0	144	0	0
T329	0	35	0	0
T330	0	29	0	0
T331	0	63	0	0
T332	0	160	0	0
T333	0	141	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	3030	0	0
T6	676357	32	0	0
T7	97039	0	0	0
T10	13504	0	0	0
T11	531918	152	0	0
T14	0	76	0	0
T27	97822	0	0	0
T28	109865	0	0	0
T51	24475	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T288	0	81	0	0
T289	0	151	0	0
T329	0	23	0	0
T330	0	60	0	0
T331	0	51	0	0
T332	0	141	0	0
T333	0	103	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	2070	0	0
T6	676357	43	0	0
T7	97039	0	0	0
T10	13504	0	0	0
T11	531918	113	0	0
T14	0	51	0	0
T27	97822	0	0	0
T28	109865	0	0	0
T51	24475	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T288	0	71	0	0
T289	0	156	0	0
T329	0	49	0	0
T330	0	58	0	0
T331	0	35	0	0
T332	0	138	0	0
T333	0	79	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	1367	0	0
T6	676357	17	0	0
T7	97039	0	0	0
T10	13504	0	0	0
T11	531918	110	0	0
T14	0	20	0	0
T27	97822	0	0	0
T28	109865	0	0	0
T51	24475	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T288	0	44	0	0
T289	0	59	0	0
T329	0	34	0	0
T330	0	38	0	0
T331	0	46	0	0
T332	0	125	0	0
T333	0	98	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	1691	0	0
T6	676357	29	0	0
T7	97039	0	0	0
T10	13504	0	0	0
T11	531918	123	0	0
T14	0	36	0	0
T27	97822	0	0	0
T28	109865	0	0	0
T51	24475	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T288	0	48	0	0
T289	0	108	0	0
T329	0	46	0	0
T330	0	44	0	0
T331	0	47	0	0
T332	0	121	0	0
T333	0	126	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	4244	0	0
T6	676357	93	0	0
T7	97039	0	0	0
T10	13504	0	0	0
T11	531918	139	0	0
T14	0	68	0	0
T27	97822	0	0	0
T28	109865	0	0	0
T51	24475	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T288	0	92	0	0
T289	0	132	0	0
T329	0	32	0	0
T330	0	49	0	0
T331	0	55	0	0
T332	0	109	0	0
T333	0	141	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	5388	0	0
T5	851278	28	0	0
T6	676357	46	0	0
T7	97039	0	0	0
T9	9382	0	0	0
T10	13504	0	0	0
T11	531918	151	0	0
T13	0	9	0	0
T14	0	33	0	0
T27	97822	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T139	0	21	0	0
T299	0	3	0	0
T329	0	23	0	0
T330	0	20	0	0
T334	0	76	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	2929	0	0
T6	676357	54	0	0
T7	97039	0	0	0
T10	13504	0	0	0
T11	531918	120	0	0
T14	0	38	0	0
T27	97822	0	0	0
T28	109865	0	0	0
T51	24475	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T288	0	49	0	0
T289	0	93	0	0
T329	0	46	0	0
T330	0	42	0	0
T331	0	60	0	0
T332	0	138	0	0
T333	0	76	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	2856	0	0
T6	676357	35	0	0
T7	97039	0	0	0
T10	13504	0	0	0
T11	531918	129	0	0
T14	0	55	0	0
T27	97822	0	0	0
T28	109865	0	0	0
T51	24475	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T288	0	61	0	0
T289	0	181	0	0
T329	0	46	0	0
T330	0	21	0	0
T331	0	43	0	0
T332	0	125	0	0
T333	0	103	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	2892	0	0
T6	676357	54	0	0
T7	97039	0	0	0
T10	13504	0	0	0
T11	531918	115	0	0
T14	0	22	0	0
T27	97822	0	0	0
T28	109865	0	0	0
T51	24475	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T288	0	77	0	0
T289	0	118	0	0
T329	0	16	0	0
T330	0	43	0	0
T331	0	80	0	0
T332	0	147	0	0
T333	0	130	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452088886	2822	0	0
T6	676357	58	0	0
T7	97039	0	0	0
T10	13504	0	0	0
T11	531918	111	0	0
T14	0	49	0	0
T27	97822	0	0	0
T28	109865	0	0	0
T51	24475	0	0	0
T54	14335	0	0	0
T109	29967	0	0	0
T110	33208	0	0	0
T288	0	83	0	0
T289	0	156	0	0
T329	0	10	0	0
T330	0	28	0	0
T331	0	45	0	0
T332	0	129	0	0
T333	0	77	0	0