Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	63.24			63.24
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	68.38			68.38
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	68.38			68.38
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	69.12			69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	69.85			69.85
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	75.00			75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	77.21			77.21
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	77.94			77.94
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	85.29			85.29
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	86.76			86.76
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	89.71			89.71
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.24			63.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.24			63.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.38			68.38

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.38			68.38

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.38			68.38

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.38			68.38

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.12			69.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.12			69.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.85			69.85

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.85			69.85

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.21			77.21

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.21			77.21

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.94			77.94

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.94			77.94

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.29			85.29

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.29			85.29

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.76			86.76

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.76			86.76

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.71			89.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.71			89.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T2,T5,T27	Yes	T2,T5,T109	INPUT
data_o[63:0]	Yes	Yes	T2,T5,T27	Yes	T2,T5,T109	OUTPUT
syndrome_o[2:0]	Yes	Yes	T146,T162,T163	Yes	T146,T162,T163	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T146,*T162,*T163	Yes	T146,T162,T163	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	172	63.24
Total Bits 0->1	136	86	63.24
Total Bits 1->0	136	86	63.24

Ports	2	0	0.00
Port Bits	272	172	63.24
Port Bits 0->1	136	86	63.24
Port Bits 1->0	136	86	63.24

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[3:0]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[5:4]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[7]	No	No		No		INPUT
data_i[8]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[9]	No	No		No		INPUT
data_i[13:10]	Yes	Yes	T5,T27,T51	Yes	T2,T4,T5	INPUT
data_i[14]	No	No		No		INPUT
data_i[17:15]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[19:18]	No	No		No		INPUT
data_i[21:20]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[22]	No	No		No		INPUT
data_i[23]	Yes	Yes	*T5,*T27,*T51	Yes	T4,T5,T27	INPUT
data_i[26:24]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T5,T27,T51	Yes	T4,T5,T27	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[32:31]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[33]	No	No		No		INPUT
data_i[35:34]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[38:36]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T5,*T27,*T51	Yes	T5,T27,T51	INPUT
data_i[40]	No	No		No		INPUT
data_i[49:41]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_i[50]	No	No		No		INPUT
data_i[52:51]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[56:53]	No	No		No		INPUT
data_i[58:57]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[60:59]	No	No		No		INPUT
data_i[71:61]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_o[3:0]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[5:4]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[8]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[13:10]	Yes	Yes	T5,T27,T51	Yes	T2,T4,T5	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[17:15]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[19:18]	No	No		No		OUTPUT
data_o[21:20]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[23]	Yes	Yes	*T5,*T27,*T51	Yes	T4,T5,T27	OUTPUT
data_o[26:24]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T5,T27,T51	Yes	T4,T5,T27	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[32:31]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[35:34]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[38:36]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T5,*T27,*T51	Yes	T5,T27,T51	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[49:41]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[52:51]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[56:53]	No	No		No		OUTPUT
data_o[58:57]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[60:59]	No	No		No		OUTPUT
data_o[63:61]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	186	68.38
Total Bits 0->1	136	93	68.38
Total Bits 1->0	136	93	68.38

Ports	2	0	0.00
Port Bits	272	186	68.38
Port Bits 0->1	136	93	68.38
Port Bits 1->0	136	93	68.38

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[1]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T5,T27	INPUT
data_i[3:2]	No	No		No		INPUT
data_i[4]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T5,T27	INPUT
data_i[5]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[7]	No	No		No		INPUT
data_i[10:8]	Yes	Yes	T2,T5,T27	Yes	T2,T5,T27	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[23:17]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[24]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[27:26]	No	No		No		INPUT
data_i[33:28]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[35:34]	No	No		No		INPUT
data_i[36]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[37]	No	No		No		INPUT
data_i[40:38]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[41]	No	No		No		INPUT
data_i[45:42]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[46]	No	No		No		INPUT
data_i[48:47]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[49]	No	No		No		INPUT
data_i[51:50]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[53:52]	No	No		No		INPUT
data_i[59:54]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_i[60]	No	No		No		INPUT
data_i[62:61]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[63]	No	No		No		INPUT
data_i[67:64]	Yes	Yes	*T5,*T27,*T28	Yes	T2,T4,T5	INPUT
data_i[68]	No	No		No		INPUT
data_i[71:69]	Yes	Yes	T2,T4,T5	Yes	T2,T5,T27	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[1]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T5,T27	OUTPUT
data_o[3:2]	No	No		No		OUTPUT
data_o[4]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T5,T27	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[10:8]	Yes	Yes	T2,T5,T27	Yes	T2,T5,T27	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[23:17]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[27:26]	No	No		No		OUTPUT
data_o[33:28]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[35:34]	No	No		No		OUTPUT
data_o[36]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[40:38]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[45:42]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[48:47]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[51:50]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[53:52]	No	No		No		OUTPUT
data_o[59:54]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[62:61]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	186	68.38
Total Bits 0->1	136	93	68.38
Total Bits 1->0	136	93	68.38

Ports	2	0	0.00
Port Bits	272	186	68.38
Port Bits 0->1	136	93	68.38
Port Bits 1->0	136	93	68.38

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[5:0]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[6]	No	No		No		INPUT
data_i[9:7]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[10]	No	No		No		INPUT
data_i[12:11]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[13]	No	No		No		INPUT
data_i[14]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[17]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[20:18]	No	No		No		INPUT
data_i[21]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[22]	No	No		No		INPUT
data_i[31:23]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[32]	No	No		No		INPUT
data_i[34:33]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[37:35]	No	No		No		INPUT
data_i[42:38]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[43]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[48:47]	No	No		No		INPUT
data_i[50:49]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[53:51]	No	No		No		INPUT
data_i[59:54]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[60]	No	No		No		INPUT
data_i[61]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[62]	No	No		No		INPUT
data_i[68:63]	Yes	Yes	T5,*T27,*T51	Yes	T2,T4,T5	INPUT
data_i[69]	No	No		No		INPUT
data_i[71:70]	Yes	Yes	T5,T127,T122	Yes	T5,T127,T122	INPUT
data_o[5:0]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[9:7]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[12:11]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[14]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[17]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[20:18]	No	No		No		OUTPUT
data_o[21]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[31:23]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[34:33]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[37:35]	No	No		No		OUTPUT
data_o[42:38]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[48:47]	No	No		No		OUTPUT
data_o[50:49]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[53:51]	No	No		No		OUTPUT
data_o[59:54]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[61]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[62]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T5,T27,T51	Yes	T2,T4,T5	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	188	69.12
Total Bits 0->1	136	94	69.12
Total Bits 1->0	136	94	69.12

Ports	2	0	0.00
Port Bits	272	188	69.12
Port Bits 0->1	136	94	69.12
Port Bits 1->0	136	94	69.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[2]	No	No		No		INPUT
data_i[4:3]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[5]	No	No		No		INPUT
data_i[9:6]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[10]	No	No		No		INPUT
data_i[11]	Yes	Yes	*T5,*T27,*T51	Yes	T2,T4,T5	INPUT
data_i[12]	No	No		No		INPUT
data_i[13]	Yes	Yes	*T5,*T27,*T51	Yes	T2,T4,T5	INPUT
data_i[14]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T5,*T27,*T51	Yes	T2,T4,T5	INPUT
data_i[16]	No	No		No		INPUT
data_i[19:17]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[21:20]	No	No		No		INPUT
data_i[23:22]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[24]	No	No		No		INPUT
data_i[31:25]	Yes	Yes	T5,T27,T51	Yes	T2,T4,T5	INPUT
data_i[32]	No	No		No		INPUT
data_i[34:33]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[35]	No	No		No		INPUT
data_i[37:36]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[38]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T5,*T27,*T51	Yes	T2,T4,T5	INPUT
data_i[40]	No	No		No		INPUT
data_i[41]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[43:42]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T5,T27,T51	Yes	T2,T4,T5	INPUT
data_i[47]	No	No		No		INPUT
data_i[49:48]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[51:50]	No	No		No		INPUT
data_i[57:52]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[58]	No	No		No		INPUT
data_i[59]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[60]	No	No		No		INPUT
data_i[62:61]	Yes	Yes	T5,T27,T51	Yes	T2,T4,T5	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_o[1:0]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[4:3]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[9:6]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[11]	Yes	Yes	*T5,*T27,*T51	Yes	T2,T4,T5	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[13]	Yes	Yes	*T5,*T27,*T51	Yes	T2,T4,T5	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T5,*T27,*T51	Yes	T2,T4,T5	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[19:17]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[21:20]	No	No		No		OUTPUT
data_o[23:22]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[31:25]	Yes	Yes	T5,T27,T51	Yes	T2,T4,T5	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[34:33]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[37:36]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T5,*T27,*T51	Yes	T2,T4,T5	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[41]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[43:42]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T5,T27,T51	Yes	T2,T4,T5	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[49:48]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[51:50]	No	No		No		OUTPUT
data_o[57:52]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[59]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[62:61]	Yes	Yes	T5,T27,T51	Yes	T2,T4,T5	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	190	69.85
Total Bits 0->1	136	95	69.85
Total Bits 1->0	136	95	69.85

Ports	2	0	0.00
Port Bits	272	190	69.85
Port Bits 0->1	136	95	69.85
Port Bits 1->0	136	95	69.85

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[6:1]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[14:9]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[15]	No	No		No		INPUT
data_i[18:16]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_i[19]	No	No		No		INPUT
data_i[22:20]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[24:23]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[26]	No	No		No		INPUT
data_i[27]	Yes	Yes	*T5,*T27,*T51	Yes	T5,T27,T51	INPUT
data_i[29:28]	No	No		No		INPUT
data_i[34:30]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[35]	No	No		No		INPUT
data_i[38:36]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_i[39]	No	No		No		INPUT
data_i[42:40]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_i[45:43]	No	No		No		INPUT
data_i[47:46]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[48]	No	No		No		INPUT
data_i[49]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[50]	No	No		No		INPUT
data_i[51]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[52]	No	No		No		INPUT
data_i[54:53]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_i[55]	No	No		No		INPUT
data_i[58:56]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_i[59]	No	No		No		INPUT
data_i[64:60]	Yes	Yes	T5,T27,*T51	Yes	T5,T27,T51	INPUT
data_i[65]	No	No		No		INPUT
data_i[71:66]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[6:1]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[14:9]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[18:16]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[22:20]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[24:23]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[27]	Yes	Yes	*T5,*T27,*T51	Yes	T5,T27,T51	OUTPUT
data_o[29:28]	No	No		No		OUTPUT
data_o[34:30]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[38:36]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[42:40]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
data_o[45:43]	No	No		No		OUTPUT
data_o[47:46]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[49]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[51]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[54:53]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[58:56]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[63:60]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	204	75.00
Total Bits 0->1	136	102	75.00
Total Bits 1->0	136	102	75.00

Ports	2	0	0.00
Port Bits	272	204	75.00
Port Bits 0->1	136	102	75.00
Port Bits 1->0	136	102	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[3:1]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[4]	No	No		No		INPUT
data_i[8:5]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[9]	No	No		No		INPUT
data_i[10]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[27:17]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[32:28]	No	No		No		INPUT
data_i[41:33]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[42]	No	No		No		INPUT
data_i[46:43]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[47]	No	No		No		INPUT
data_i[51:48]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[52]	No	No		No		INPUT
data_i[54:53]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[55]	No	No		No		INPUT
data_i[61:56]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[63:62]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[3:1]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[8:5]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[10]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[27:17]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[32:28]	No	No		No		OUTPUT
data_o[41:33]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[46:43]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[51:48]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[54:53]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[61:56]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[63:62]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	210	77.21
Total Bits 0->1	136	105	77.21
Total Bits 1->0	136	105	77.21

Ports	2	0	0.00
Port Bits	272	210	77.21
Port Bits 0->1	136	105	77.21
Port Bits 1->0	136	105	77.21

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[1]	No	No		No		INPUT
data_i[4:2]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[5]	No	No		No		INPUT
data_i[7:6]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[8]	No	No		No		INPUT
data_i[12:9]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[13]	No	No		No		INPUT
data_i[17:14]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_i[18]	No	No		No		INPUT
data_i[21:19]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[24:22]	No	No		No		INPUT
data_i[28:25]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[38:31]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[39]	No	No		No		INPUT
data_i[50:40]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[52:51]	No	No		No		INPUT
data_i[55:53]	Yes	Yes	T5,T103,T104	Yes	T5,T103,T104	INPUT
data_i[56]	No	No		No		INPUT
data_i[60:57]	Yes	Yes	*T2,T5,*T27	Yes	T2,T4,T5	INPUT
data_i[61]	No	No		No		INPUT
data_i[69:62]	Yes	Yes	*T2,T5,*T27	Yes	T2,T4,T5	INPUT
data_i[70]	No	No		No		INPUT
data_i[71]	Yes	Yes	T5,T51,T103	Yes	T5,T51,T103	INPUT
data_o[0]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[4:2]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[7:6]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[12:9]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[17:14]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[21:19]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[24:22]	No	No		No		OUTPUT
data_o[28:25]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[38:31]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[50:40]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[52:51]	No	No		No		OUTPUT
data_o[55:53]	Yes	Yes	T5,T103,T104	Yes	T5,T103,T104	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[60:57]	Yes	Yes	*T2,T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	212	77.94
Total Bits 0->1	136	106	77.94
Total Bits 1->0	136	106	77.94

Ports	2	0	0.00
Port Bits	272	212	77.94
Port Bits 0->1	136	106	77.94
Port Bits 1->0	136	106	77.94

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_i[2]	No	No		No		INPUT
data_i[7:3]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[8]	No	No		No		INPUT
data_i[9]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[11:10]	No	No		No		INPUT
data_i[13:12]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[14]	No	No		No		INPUT
data_i[16:15]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[17]	No	No		No		INPUT
data_i[18]	Yes	Yes	*T5,*T27,*T51	Yes	T5,T27,T51	INPUT
data_i[19]	No	No		No		INPUT
data_i[28:20]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[36:31]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_i[37]	No	No		No		INPUT
data_i[45:38]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_i[46]	No	No		No		INPUT
data_i[47]	Yes	Yes	*T93	Yes	T93	INPUT
data_i[48]	No	No		No		INPUT
data_i[53:49]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_i[54]	No	No		No		INPUT
data_i[56:55]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[57]	No	No		No		INPUT
data_i[60:58]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_o[1:0]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[7:3]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[9]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[11:10]	No	No		No		OUTPUT
data_o[13:12]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[16:15]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[18]	Yes	Yes	*T5,*T27,*T51	Yes	T5,T27,T51	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[28:20]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[36:31]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[45:38]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[47]	Yes	Yes	*T93	Yes	T93	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[53:49]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[56:55]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[60:58]	Yes	Yes	*T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	232	85.29
Total Bits 0->1	136	116	85.29
Total Bits 1->0	136	116	85.29

Ports	2	0	0.00
Port Bits	272	232	85.29
Port Bits 0->1	136	116	85.29
Port Bits 1->0	136	116	85.29

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[6:0]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[7]	No	No		No		INPUT
data_i[9:8]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[11:10]	No	No		No		INPUT
data_i[19:12]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[20]	No	No		No		INPUT
data_i[22:21]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[23]	No	No		No		INPUT
data_i[27:24]	Yes	Yes	*T91,*T2,*T5	Yes	T91,T2,T4	INPUT
data_i[28]	No	No		No		INPUT
data_i[36:29]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[37]	No	No		No		INPUT
data_i[43:38]	Yes	Yes	*T87,*T2,*T5	Yes	T87,T2,T4	INPUT
data_i[44]	No	No		No		INPUT
data_i[47:45]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[48]	No	No		No		INPUT
data_i[58:49]	Yes	Yes	*T87,*T2,*T5	Yes	T87,T2,T4	INPUT
data_i[59]	No	No		No		INPUT
data_i[71:60]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_o[6:0]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[9:8]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[11:10]	No	No		No		OUTPUT
data_o[19:12]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[22:21]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[27:24]	Yes	Yes	*T91,*T2,*T5	Yes	T91,T2,T4	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[36:29]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[43:38]	Yes	Yes	*T87,*T2,*T5	Yes	T87,T2,T4	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[47:45]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[58:49]	Yes	Yes	*T87,*T2,*T5	Yes	T87,T2,T4	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[63:60]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	236	86.76
Total Bits 0->1	136	118	86.76
Total Bits 1->0	136	118	86.76

Ports	2	0	0.00
Port Bits	272	236	86.76
Port Bits 0->1	136	118	86.76
Port Bits 1->0	136	118	86.76

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	No	No		No		INPUT
data_i[12:2]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[13]	No	No		No		INPUT
data_i[14]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[15]	No	No		No		INPUT
data_i[20:16]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[22:21]	No	No		No		INPUT
data_i[24:23]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[25]	No	No		No		INPUT
data_i[36:26]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[37]	No	No		No		INPUT
data_i[54:38]	Yes	Yes	*T86,*T2,*T5	Yes	T86,T2,T4	INPUT
data_i[55]	No	No		No		INPUT
data_i[71:56]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_o[1:0]	No	No		No		OUTPUT
data_o[12:2]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[14]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[20:16]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[22:21]	No	No		No		OUTPUT
data_o[24:23]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[36:26]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[54:38]	Yes	Yes	*T86,*T2,*T5	Yes	T86,T2,T4	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[63:56]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	244	89.71
Total Bits 0->1	136	122	89.71
Total Bits 1->0	136	122	89.71

Ports	2	0	0.00
Port Bits	272	244	89.71
Port Bits 0->1	136	122	89.71
Port Bits 1->0	136	122	89.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[4:0]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[5]	No	No		No		INPUT
data_i[7:6]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[8]	No	No		No		INPUT
data_i[10:9]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[11]	No	No		No		INPUT
data_i[13:12]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_i[14]	No	No		No		INPUT
data_i[25:15]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[26]	No	No		No		INPUT
data_i[44:27]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	INPUT
data_i[45]	No	No		No		INPUT
data_i[46]	Yes	Yes	*T90	Yes	T90	INPUT
data_i[47]	No	No		No		INPUT
data_i[71:48]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	INPUT
data_o[4:0]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[7:6]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[10:9]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[13:12]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[25:15]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[44:27]	Yes	Yes	*T2,*T5,*T27	Yes	T2,T4,T5	OUTPUT
data_o[45]	No	No		No		OUTPUT
data_o[46]	Yes	Yes	*T90	Yes	T90	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[63:48]	Yes	Yes	T2,T5,T27	Yes	T2,T4,T5	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T51,T28	Yes	T5,T109,T51	INPUT
data_o[63:0]	Yes	Yes	T5,T51,T28	Yes	T5,T109,T51	OUTPUT
syndrome_o[2:0]	Yes	Yes	T158,T160	Yes	T158,T160	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T158,*T160	Yes	T158,T160	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T5,T103	Yes	T2,T5,T103	INPUT
data_o[63:0]	Yes	Yes	T2,T5,T103	Yes	T2,T5,T103	OUTPUT
syndrome_o[2:0]	Yes	Yes	T146,T162,T163	Yes	T146,T162,T163	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T146,*T162,*T163	Yes	T146,T162,T163	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T5,T103	Yes	T2,T5,T109	INPUT
data_o[63:0]	Yes	Yes	T2,T5,T103	Yes	T2,T5,T109	OUTPUT
syndrome_o[2:0]	Yes	Yes	T146,T163,T158	Yes	T146,T163,T158	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T146,*T163,*T158	Yes	T146,T163,T158	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	INPUT
data_o[63:0]	Yes	Yes	T5,T27,T51	Yes	T5,T27,T51	OUTPUT
syndrome_o[2:0]	Yes	Yes	T158,T159	Yes	T158,T159	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T158,*T159	Yes	T158,T159	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T138,T210	Yes	T5,T138,T210	INPUT
data_o[63:0]	Yes	Yes	T5,T138,T210	Yes	T5,T138,T210	OUTPUT
syndrome_o[2:0]	Yes	Yes	T146,T163,T158	Yes	T146,T163,T158	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T146,*T163,*T158	Yes	T146,T163,T158	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T211,T64,T107	Yes	T211,T64,T107	INPUT
data_o[63:0]	Yes	Yes	T211,T64,T107	Yes	T211,T64,T107	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T156,T66	Yes	T5,T255,T156	INPUT
data_o[63:0]	Yes	Yes	T5,T156,T66	Yes	T5,T255,T156	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T40,T13	Yes	T5,T40,T13	INPUT
data_o[63:0]	Yes	Yes	T5,T40,T13	Yes	T5,T40,T13	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T107,T31	Yes	T5,T107,T31	INPUT
data_o[63:0]	Yes	Yes	T5,T107,T31	Yes	T5,T107,T31	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T104,T107,T122	Yes	T104,T107,T122	INPUT
data_o[63:0]	Yes	Yes	T104,T107,T122	Yes	T104,T107,T122	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T31,T156,T122	Yes	T31,T156,T122	INPUT
data_o[63:0]	Yes	Yes	T31,T156,T122	Yes	T31,T156,T122	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T205,T32	Yes	T5,T205,T32	INPUT
data_o[63:0]	Yes	Yes	T5,T205,T32	Yes	T5,T205,T32	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T209,T261	Yes	T5,T209,T222	INPUT
data_o[63:0]	Yes	Yes	T5,T209,T261	Yes	T5,T209,T222	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T27,T13	Yes	T4,T5,T27	INPUT
data_o[63:0]	Yes	Yes	T5,T27,T13	Yes	T4,T5,T27	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T40,T13	Yes	T5,T109,T40	INPUT
data_o[63:0]	Yes	Yes	T5,T40,T13	Yes	T5,T109,T40	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T103,T13	Yes	T5,T103,T13	INPUT
data_o[63:0]	Yes	Yes	T5,T103,T13	Yes	T5,T103,T13	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T5,T54	Yes	T1,T5,T54	INPUT
data_o[63:0]	Yes	Yes	T1,T5,T54	Yes	T1,T5,T54	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T10,T27	Yes	T4,T5,T10	INPUT
data_o[63:0]	Yes	Yes	T5,T10,T27	Yes	T4,T5,T10	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T10,T27	Yes	T5,T10,T27	INPUT
data_o[63:0]	Yes	Yes	T5,T10,T27	Yes	T5,T10,T27	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR