Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7168279	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6890155

1

T1

700

T2

79

T3

216

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8410549	1			T1	2638		T2	1290		T3	403
values[0x0]	2166875	1			T1	124		T2	17		T3	129
values[0x1]	3481010	1			T1	132		T2	12		T3	126

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4707229	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9351205

1

T1

1346

T2

445

T3

329

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55423	1			T2	6		T6	2		T4	24
valid_sources[0x01]	53199	1			T2	2		T6	4		T4	34
valid_sources[0x02]	49821	1			T2	4		T6	1		T4	27
valid_sources[0x03]	48014	1			T2	4		T6	2		T4	14
valid_sources[0x04]	50837	1			T2	3		T4	30		T11	30
valid_sources[0x05]	47866	1			T2	4		T6	4		T4	25
valid_sources[0x06]	133090	1			T2	1		T6	4		T4	31
valid_sources[0x07]	49169	1			T2	5		T6	2		T4	30
valid_sources[0x08]	62691	1			T2	8		T6	2		T4	21
valid_sources[0x09]	53462	1			T2	5		T6	3		T4	24
valid_sources[0x0a]	50401	1			T2	4		T6	4		T4	29
valid_sources[0x0b]	48242	1			T2	8		T6	5		T4	25
valid_sources[0x0c]	49083	1			T2	5		T6	1		T4	32
valid_sources[0x0d]	51404	1			T2	7		T4	27		T11	1
valid_sources[0x0e]	48067	1			T2	5		T6	5		T4	35
valid_sources[0x0f]	63172	1			T2	5		T4	25		T11	20
valid_sources[0x10]	58567	1			T2	3		T6	2		T4	29
valid_sources[0x11]	50131	1			T2	3		T6	1		T4	20
valid_sources[0x12]	50078	1			T2	5		T6	1		T4	33
valid_sources[0x13]	50314	1			T2	7		T4	33		T11	5
valid_sources[0x14]	48474	1			T2	6		T6	2		T4	28
valid_sources[0x15]	51146	1			T2	4		T6	6		T4	25
valid_sources[0x16]	60860	1			T2	6		T4	25		T11	13
valid_sources[0x17]	48273	1			T2	3		T4	16		T11	17
valid_sources[0x18]	56381	1			T2	6		T6	2		T4	40
valid_sources[0x19]	49509	1			T2	5		T4	31		T11	7
valid_sources[0x1a]	64903	1			T2	5		T4	30		T11	16
valid_sources[0x1b]	66249	1			T2	5		T4	24		T11	14
valid_sources[0x1c]	48944	1			T2	5		T6	3		T4	22
valid_sources[0x1d]	54867	1			T2	3		T6	2		T4	26
valid_sources[0x1e]	48560	1			T2	6		T6	2		T4	26
valid_sources[0x1f]	50103	1			T2	5		T6	2		T4	23
valid_sources[0x20]	50774	1			T2	2		T6	1		T4	24
valid_sources[0x21]	57022	1			T2	8		T6	1		T4	31
valid_sources[0x22]	50476	1			T2	5		T4	20		T11	16
valid_sources[0x23]	55116	1			T2	4		T6	1		T4	26
valid_sources[0x24]	53768	1			T2	7		T6	1		T4	24
valid_sources[0x25]	49895	1			T2	6		T6	3		T4	29
valid_sources[0x26]	49074	1			T2	4		T6	4		T4	21
valid_sources[0x27]	55327	1			T2	5		T6	1		T4	17
valid_sources[0x28]	57930	1			T2	4		T6	3		T4	30
valid_sources[0x29]	67838	1			T2	7		T6	1		T4	17
valid_sources[0x2a]	63123	1			T2	4		T6	2		T4	25
valid_sources[0x2b]	52562	1			T2	2		T6	3		T4	15
valid_sources[0x2c]	47304	1			T2	8		T6	1		T4	30
valid_sources[0x2d]	55842	1			T2	1		T6	2		T4	24
valid_sources[0x2e]	48166	1			T2	5		T6	2		T4	36
valid_sources[0x2f]	55892	1			T2	4		T6	1		T4	28
valid_sources[0x30]	54213	1			T2	6		T4	26		T11	35
valid_sources[0x31]	50475	1			T2	2		T4	24		T11	21
valid_sources[0x32]	47773	1			T2	2		T6	1		T4	20
valid_sources[0x33]	49918	1			T2	10		T6	2		T4	24
valid_sources[0x34]	50067	1			T2	7		T6	1		T4	29
valid_sources[0x35]	52150	1			T2	2		T6	3		T4	30
valid_sources[0x36]	56654	1			T2	2		T6	8		T4	20
valid_sources[0x37]	56186	1			T2	7		T6	2		T4	27
valid_sources[0x38]	49345	1			T2	4		T4	27		T11	22
valid_sources[0x39]	50815	1			T2	9		T6	1		T4	35
valid_sources[0x3a]	48664	1			T2	3		T6	3		T4	26
valid_sources[0x3b]	50568	1			T2	7		T4	26		T11	14
valid_sources[0x3c]	47465	1			T2	3		T6	2		T4	33
valid_sources[0x3d]	54125	1			T2	10		T6	4		T4	29
valid_sources[0x3e]	48647	1			T2	6		T6	2		T4	22
valid_sources[0x3f]	52057	1			T2	5		T6	6		T4	28
valid_sources[0x40]	56573	1			T2	9		T4	38		T11	6
valid_sources[0x41]	47139	1			T2	7		T6	3		T4	22
valid_sources[0x42]	47140	1			T2	8		T6	2		T4	32
valid_sources[0x43]	49455	1			T2	7		T4	21		T11	13
valid_sources[0x44]	47681	1			T2	1		T6	2		T4	32
valid_sources[0x45]	48470	1			T2	6		T4	26		T11	21
valid_sources[0x46]	58499	1			T2	6		T4	30		T11	14
valid_sources[0x47]	55896	1			T2	4		T4	27		T11	2
valid_sources[0x48]	50256	1			T2	8		T4	27		T11	3
valid_sources[0x49]	48101	1			T2	6		T6	2		T4	29
valid_sources[0x4a]	51125	1			T2	6		T6	2		T4	23
valid_sources[0x4b]	49714	1			T2	3		T4	25		T11	20
valid_sources[0x4c]	49199	1			T2	4		T4	20		T11	6
valid_sources[0x4d]	48747	1			T2	7		T6	6		T4	20
valid_sources[0x4e]	54953	1			T2	4		T6	1		T4	24
valid_sources[0x4f]	48240	1			T2	5		T6	7		T4	24
valid_sources[0x50]	49439	1			T2	9		T4	20		T11	9
valid_sources[0x51]	52537	1			T2	6		T6	1		T4	29
valid_sources[0x52]	49213	1			T2	8		T6	1		T4	22
valid_sources[0x53]	52715	1			T2	4		T4	16		T11	7
valid_sources[0x54]	45878	1			T2	2		T6	2		T4	38
valid_sources[0x55]	52371	1			T2	4		T4	20		T11	2
valid_sources[0x56]	62959	1			T2	2		T6	3		T4	29
valid_sources[0x57]	50868	1			T2	9		T6	3		T4	34
valid_sources[0x58]	54543	1			T2	2		T6	1		T4	20
valid_sources[0x59]	57109	1			T2	4		T6	1		T4	23
valid_sources[0x5a]	49994	1			T2	5		T6	1		T4	25
valid_sources[0x5b]	48094	1			T2	6		T6	4		T4	21
valid_sources[0x5c]	48711	1			T2	2		T6	3		T4	23
valid_sources[0x5d]	51216	1			T2	6		T4	30		T11	3
valid_sources[0x5e]	49189	1			T2	6		T6	3		T4	37
valid_sources[0x5f]	57570	1			T2	10		T6	3		T4	32
valid_sources[0x60]	48831	1			T2	6		T6	2		T4	24
valid_sources[0x61]	47693	1			T2	3		T6	1		T4	18
valid_sources[0x62]	53611	1			T2	3		T6	4		T4	26
valid_sources[0x63]	53703	1			T2	5		T6	3		T4	30
valid_sources[0x64]	55332	1			T2	8		T6	3		T4	20
valid_sources[0x65]	54600	1			T2	5		T6	4		T4	27
valid_sources[0x66]	59590	1			T2	7		T4	34		T11	7
valid_sources[0x67]	51032	1			T2	8		T6	2		T4	28
valid_sources[0x68]	48763	1			T2	3		T6	1		T4	27
valid_sources[0x69]	56655	1			T2	1		T4	21		T11	15
valid_sources[0x6a]	51000	1			T2	8		T6	4		T4	32
valid_sources[0x6b]	50729	1			T2	6		T3	658		T6	1
valid_sources[0x6c]	60538	1			T2	6		T6	2		T4	37
valid_sources[0x6d]	48204	1			T2	1		T6	1		T4	42
valid_sources[0x6e]	53630	1			T2	2		T6	1		T4	34
valid_sources[0x6f]	50717	1			T2	9		T6	3		T4	32
valid_sources[0x70]	53774	1			T2	9		T6	1		T4	36
valid_sources[0x71]	129377	1			T2	2		T6	3		T4	23
valid_sources[0x72]	50072	1			T2	5		T6	1		T4	29
valid_sources[0x73]	52801	1			T2	7		T6	1		T4	23
valid_sources[0x74]	51784	1			T2	2		T4	26		T11	1
valid_sources[0x75]	49073	1			T2	5		T4	29		T11	8
valid_sources[0x76]	53238	1			T2	6		T6	1		T4	27
valid_sources[0x77]	50561	1			T2	8		T6	1		T4	26
valid_sources[0x78]	49471	1			T2	6		T6	2		T4	30
valid_sources[0x79]	60873	1			T2	5		T6	7		T4	24
valid_sources[0x7a]	49297	1			T2	6		T6	3		T4	19
valid_sources[0x7b]	54649	1			T2	3		T6	1		T4	19
valid_sources[0x7c]	57499	1			T2	5		T6	3		T4	24
valid_sources[0x7d]	48724	1			T2	4		T6	5		T4	19
valid_sources[0x7e]	50343	1			T2	5		T6	1		T4	20
valid_sources[0x7f]	61853	1			T2	6		T6	4		T4	32
valid_sources[0x80]	69408	1			T2	4		T6	2		T4	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3411528

1

T1

595

T2

69

T3

100

values[0x0]

all_enables

biggest_size

1778684

1

T1

56

T2

8

T3

67

values[0x1]

all_enables

biggest_size

1699943

1

T1

49

T2

2

T3

49

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	227197	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8173964

1

T1

160

T2

40

T9

180

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2095478	1			T1	80		T2	20		T9	90
values[0x0]	3062318	1			T1	35		T2	7		T9	47
values[0x1]	3243365	1			T1	45		T2	13		T9	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	82798	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8318363

1

T1

160

T2

40

T9

180

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32051	1			T4	2		T5	323		T7	710
valid_sources[0x01]	32076	1			T5	369		T42	2		T7	576
valid_sources[0x02]	33148	1			T12	1		T5	339		T7	37
valid_sources[0x03]	32271	1			T9	2		T5	345		T42	3
valid_sources[0x04]	33429	1			T9	1		T5	381		T17	1
valid_sources[0x05]	32258	1			T9	4		T4	4		T5	333
valid_sources[0x06]	32064	1			T1	1		T5	375		T42	2
valid_sources[0x07]	33556	1			T9	1		T12	1		T5	369
valid_sources[0x08]	32038	1			T5	376		T28	3		T7	295
valid_sources[0x09]	33391	1			T1	3		T2	1		T5	324
valid_sources[0x0a]	32744	1			T1	1		T2	1		T5	330
valid_sources[0x0b]	32230	1			T4	1		T5	366		T7	359
valid_sources[0x0c]	32484	1			T1	1		T4	1		T5	390
valid_sources[0x0d]	31754	1			T9	1		T5	340		T7	537
valid_sources[0x0e]	32969	1			T1	3		T5	377		T28	2
valid_sources[0x0f]	33774	1			T12	3		T5	387		T17	1
valid_sources[0x10]	35558	1			T5	345		T7	1099		T209	2
valid_sources[0x11]	32464	1			T9	1		T5	405		T7	404
valid_sources[0x12]	32565	1			T1	1		T5	324		T7	928
valid_sources[0x13]	32034	1			T9	1		T5	344		T7	177
valid_sources[0x14]	32565	1			T9	2		T12	2		T5	334
valid_sources[0x15]	32573	1			T2	2		T5	358		T7	376
valid_sources[0x16]	33859	1			T1	1		T5	334		T7	687
valid_sources[0x17]	33652	1			T2	1		T5	357		T7	1466
valid_sources[0x18]	33810	1			T9	3		T5	380		T28	2
valid_sources[0x19]	33134	1			T5	361		T28	1		T7	414
valid_sources[0x1a]	33098	1			T9	11		T5	350		T28	1
valid_sources[0x1b]	31619	1			T1	3		T4	3		T5	358
valid_sources[0x1c]	31280	1			T5	369		T7	527		T8	1
valid_sources[0x1d]	32231	1			T1	1		T5	331		T7	429
valid_sources[0x1e]	33959	1			T9	2		T12	2		T5	313
valid_sources[0x1f]	34097	1			T1	2		T9	2		T5	376
valid_sources[0x20]	33014	1			T1	1		T4	1		T5	387
valid_sources[0x21]	31473	1			T2	1		T5	355		T28	2
valid_sources[0x22]	33021	1			T1	1		T12	5		T5	384
valid_sources[0x23]	33150	1			T2	1		T5	346		T17	1
valid_sources[0x24]	32764	1			T9	3		T5	348		T42	1
valid_sources[0x25]	31349	1			T12	3		T5	386		T7	452
valid_sources[0x26]	32622	1			T5	333		T28	2		T7	504
valid_sources[0x27]	31489	1			T1	1		T5	356		T7	43
valid_sources[0x28]	32855	1			T5	391		T7	199		T36	3
valid_sources[0x29]	32848	1			T5	357		T7	195		T209	1
valid_sources[0x2a]	33151	1			T9	7		T4	1		T5	390
valid_sources[0x2b]	32619	1			T9	5		T5	344		T7	461
valid_sources[0x2c]	33414	1			T5	366		T7	54		T14	80
valid_sources[0x2d]	33664	1			T5	353		T17	1		T28	1
valid_sources[0x2e]	32392	1			T1	2		T2	1		T9	3
valid_sources[0x2f]	33417	1			T1	1		T5	347		T7	498
valid_sources[0x30]	33354	1			T5	368		T7	596		T36	1
valid_sources[0x31]	32466	1			T4	1		T12	1		T5	376
valid_sources[0x32]	32994	1			T12	1		T5	358		T7	339
valid_sources[0x33]	32074	1			T5	320		T17	1		T7	715
valid_sources[0x34]	32402	1			T1	2		T2	1		T5	373
valid_sources[0x35]	31920	1			T12	1		T5	341		T7	438
valid_sources[0x36]	32289	1			T9	1		T4	2		T5	379
valid_sources[0x37]	31231	1			T5	378		T17	1		T7	807
valid_sources[0x38]	32445	1			T9	2		T5	363		T42	3
valid_sources[0x39]	32532	1			T9	1		T5	349		T7	424
valid_sources[0x3a]	32741	1			T5	367		T7	173		T36	1
valid_sources[0x3b]	32792	1			T5	329		T7	301		T37	1
valid_sources[0x3c]	32954	1			T5	371		T7	1219		T209	1
valid_sources[0x3d]	32247	1			T1	2		T5	382		T7	693
valid_sources[0x3e]	34126	1			T2	2		T4	1		T12	3
valid_sources[0x3f]	33194	1			T5	356		T7	803		T209	1
valid_sources[0x40]	32521	1			T2	2		T5	383		T7	831
valid_sources[0x41]	34258	1			T5	346		T7	1445		T37	1
valid_sources[0x42]	32177	1			T9	2		T4	1		T5	343
valid_sources[0x43]	34101	1			T12	2		T5	338		T28	2
valid_sources[0x44]	32229	1			T5	346		T7	84		T209	1
valid_sources[0x45]	35278	1			T5	356		T7	409		T36	1
valid_sources[0x46]	33425	1			T1	1		T2	1		T5	374
valid_sources[0x47]	31719	1			T2	2		T9	3		T5	352
valid_sources[0x48]	32253	1			T5	351		T7	292		T36	4
valid_sources[0x49]	33625	1			T1	3		T2	2		T9	1
valid_sources[0x4a]	34428	1			T9	2		T5	387		T7	715
valid_sources[0x4b]	32598	1			T5	367		T28	3		T7	484
valid_sources[0x4c]	31881	1			T1	1		T5	352		T7	738
valid_sources[0x4d]	32319	1			T9	1		T5	336		T28	3
valid_sources[0x4e]	33438	1			T4	4		T5	376		T7	307
valid_sources[0x4f]	33294	1			T4	2		T5	375		T7	855
valid_sources[0x50]	33471	1			T1	1		T9	1		T12	1
valid_sources[0x51]	32260	1			T5	388		T7	546		T14	77
valid_sources[0x52]	32141	1			T1	1		T5	353		T7	577
valid_sources[0x53]	32510	1			T12	2		T5	365		T42	7
valid_sources[0x54]	31872	1			T5	322		T7	235		T209	1
valid_sources[0x55]	33115	1			T5	387		T7	822		T37	2
valid_sources[0x56]	33654	1			T5	355		T7	503		T37	1
valid_sources[0x57]	32400	1			T1	1		T4	7		T5	369
valid_sources[0x58]	32110	1			T1	2		T4	2		T12	2
valid_sources[0x59]	32102	1			T4	2		T5	356		T7	1376
valid_sources[0x5a]	32377	1			T1	1		T2	1		T5	345
valid_sources[0x5b]	32936	1			T1	2		T9	3		T5	349
valid_sources[0x5c]	31885	1			T2	1		T12	3		T5	350
valid_sources[0x5d]	33252	1			T9	1		T5	359		T7	789
valid_sources[0x5e]	32788	1			T1	4		T5	369		T28	2
valid_sources[0x5f]	34331	1			T1	1		T5	351		T7	658
valid_sources[0x60]	32678	1			T5	390		T7	687		T209	1
valid_sources[0x61]	33842	1			T12	1		T5	348		T7	235
valid_sources[0x62]	32409	1			T1	6		T5	342		T7	376
valid_sources[0x63]	32408	1			T5	349		T7	623		T209	1
valid_sources[0x64]	31865	1			T1	1		T4	3		T5	390
valid_sources[0x65]	32563	1			T5	318		T7	184		T14	79
valid_sources[0x66]	33987	1			T11	160		T5	372		T7	1335
valid_sources[0x67]	32767	1			T1	3		T12	5		T5	372
valid_sources[0x68]	32508	1			T4	1		T5	387		T7	491
valid_sources[0x69]	34366	1			T1	1		T9	1		T5	344
valid_sources[0x6a]	31606	1			T1	1		T5	367		T7	196
valid_sources[0x6b]	31781	1			T4	2		T5	339		T7	516
valid_sources[0x6c]	31475	1			T5	335		T28	1		T7	165
valid_sources[0x6d]	31891	1			T1	1		T5	376		T7	276
valid_sources[0x6e]	31482	1			T1	1		T9	3		T4	2
valid_sources[0x6f]	31636	1			T5	379		T7	976		T209	1
valid_sources[0x70]	32727	1			T1	1		T5	363		T28	2
valid_sources[0x71]	32209	1			T1	1		T5	391		T7	202
valid_sources[0x72]	33890	1			T1	1		T9	1		T5	369
valid_sources[0x73]	33510	1			T1	2		T9	1		T4	1
valid_sources[0x74]	33575	1			T1	2		T5	390		T17	1
valid_sources[0x75]	32591	1			T12	1		T5	393		T7	138
valid_sources[0x76]	32140	1			T2	1		T5	372		T7	887
valid_sources[0x77]	33420	1			T1	3		T9	1		T5	358
valid_sources[0x78]	32509	1			T12	1		T5	340		T7	331
valid_sources[0x79]	31378	1			T9	1		T5	384		T7	464
valid_sources[0x7a]	32144	1			T5	357		T7	293		T209	1
valid_sources[0x7b]	32316	1			T1	1		T4	1		T5	361
valid_sources[0x7c]	32924	1			T1	1		T2	1		T9	1
valid_sources[0x7d]	32789	1			T1	1		T5	372		T42	1
valid_sources[0x7e]	34479	1			T9	2		T5	341		T7	784
valid_sources[0x7f]	33223	1			T1	2		T9	3		T5	338
valid_sources[0x80]	32876	1			T9	11		T12	1		T5	378

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2082209

1

T1

80

T2

20

T9

90

values[0x0]

all_enables

biggest_size

3046760

1

T1

35

T2

7

T9

47

values[0x1]

all_enables

biggest_size

3044995

1

T1

45

T2

13

T9

43