Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

23553119

1

T1

2194

T2

1240

T3

442

full_word

7880684

1

T1

700

T2

79

T3

216

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31433503	1			T1	2894		T2	1319		T3	658
auto[TlIntgErrCmd]	94	1			T279	9		T280	4		T281	5
auto[TlIntgErrData]	114	1			T279	6		T280	7		T281	10
auto[TlIntgErrBoth]	92	1			T279	5		T280	9		T281	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9612636

1

T1

2638

T2

1290

T3

403

auto[1]

21821167

1

T1

256

T2

29

T3

255

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6079209	1			T1	2043		T2	1221		T3	303
auto[TlIntgErrNone]	partial	auto[1]	17473635	1			T1	151		T2	19		T3	139
auto[TlIntgErrNone]	full_word	auto[0]	3533278	1			T1	595		T2	69		T3	100
auto[TlIntgErrNone]	full_word	auto[1]	4347381	1			T1	105		T2	10		T3	116
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T279	5		T280	1		T281	2
auto[TlIntgErrCmd]	partial	auto[1]	39	1			T279	2		T280	2		T281	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T280	1		T368	1		T362	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T279	2		T281	1		T366	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T280	4		T281	7		T364	3
auto[TlIntgErrData]	partial	auto[1]	50	1			T279	6		T280	1		T281	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T280	1		T364	2		T369	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T280	1		T281	1		T365	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T279	4		T280	3		T281	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T280	6		T281	2		T363	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T370	1		T366	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T279	1		-	-		-	-