Unified Coverage Report :: Module :: prim_lfsr

Module : prim_lfsr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.11			77.11

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr	77.11			77.11
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr	77.11			77.11

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.11			77.11

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.11			77.11

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_double_lfsr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.11			77.11

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.11			77.11

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_double_lfsr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	128	77.11
Total Bits 0->1	83	64	77.11
Total Bits 1->0	83	64	77.11

Ports	5	4	80.00
Port Bits	166	128	77.11
Port Bits 0->1	83	64	77.11
Port Bits 1->0	83	64	77.11

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[2:0]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[4:3]	No	No		No		INPUT
entropy_i[6:5]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[10:7]	No	No		No		INPUT
entropy_i[14:11]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[15]	No	No		No		INPUT
entropy_i[17:16]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[18]	No	No		No		INPUT
entropy_i[19]	Yes	Yes	*T15	Yes	T15	INPUT
entropy_i[20]	No	No		No		INPUT
entropy_i[24:21]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[25]	No	No		No		INPUT
entropy_i[26]	Yes	Yes	*T15	Yes	T15	INPUT
entropy_i[32:27]	No	No		No		INPUT
entropy_i[35:33]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[38:36]	No	No		No		INPUT
entropy_i[39]	Yes	Yes	T15	Yes	T15	INPUT
state_o[39:0]	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	128	77.11
Total Bits 0->1	83	64	77.11
Total Bits 1->0	83	64	77.11

Ports	5	4	80.00
Port Bits	166	128	77.11
Port Bits 0->1	83	64	77.11
Port Bits 1->0	83	64	77.11

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[2:0]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[4:3]	No	No		No		INPUT
entropy_i[6:5]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[10:7]	No	No		No		INPUT
entropy_i[14:11]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[15]	No	No		No		INPUT
entropy_i[17:16]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[18]	No	No		No		INPUT
entropy_i[19]	Yes	Yes	*T15	Yes	T15	INPUT
entropy_i[20]	No	No		No		INPUT
entropy_i[24:21]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[25]	No	No		No		INPUT
entropy_i[26]	Yes	Yes	*T15	Yes	T15	INPUT
entropy_i[32:27]	No	No		No		INPUT
entropy_i[35:33]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[38:36]	No	No		No		INPUT
entropy_i[39]	Yes	Yes	T15	Yes	T15	INPUT
state_o[39:0]	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	128	77.11
Total Bits 0->1	83	64	77.11
Total Bits 1->0	83	64	77.11

Ports	5	4	80.00
Port Bits	166	128	77.11
Port Bits 0->1	83	64	77.11
Port Bits 1->0	83	64	77.11

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[2:0]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[4:3]	No	No		No		INPUT
entropy_i[6:5]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[10:7]	No	No		No		INPUT
entropy_i[14:11]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[15]	No	No		No		INPUT
entropy_i[17:16]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[18]	No	No		No		INPUT
entropy_i[19]	Yes	Yes	*T15	Yes	T15	INPUT
entropy_i[20]	No	No		No		INPUT
entropy_i[24:21]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[25]	No	No		No		INPUT
entropy_i[26]	Yes	Yes	*T15	Yes	T15	INPUT
entropy_i[32:27]	No	No		No		INPUT
entropy_i[35:33]	Yes	Yes	T15	Yes	T15	INPUT
entropy_i[38:36]	No	No		No		INPUT
entropy_i[39]	Yes	Yes	T15	Yes	T15	INPUT
state_o[39:0]	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT

*Tests covering at least one bit in the range