Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.14		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	440337468	7383032	0	0
check_regwen_rd_A	440337468	3050	0	0
check_timeout_rd_A	440337468	2651	0	0
check_trigger_regwen_rd_A	440337468	3071	0	0
consistency_check_period_rd_A	440337468	3131	0	0
creator_sw_cfg_read_lock_rd_A	440337468	2954	0	0
direct_access_address_rd_A	440337468	2027	0	0
direct_access_wdata_0_rd_A	440337468	1314	0	0
direct_access_wdata_1_rd_A	440337468	1509	0	0
integrity_check_period_rd_A	440337468	3026	0	0
intr_enable_rd_A	440337468	3512	0	0
owner_sw_cfg_read_lock_rd_A	440337468	2798	0	0
rot_creator_auth_codesign_read_lock_rd_A	440337468	2884	0	0
rot_creator_auth_state_read_lock_rd_A	440337468	2708	0	0
vendor_test_read_lock_rd_A	440337468	2762	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	7383032	0	0
T5	281016	85847	0	0
T7	633484	131904	0	0
T8	13494	0	0	0
T14	0	15909	0	0
T16	9595	0	0	0
T17	14851	0	0	0
T18	0	267978	0	0
T19	0	104392	0	0
T20	0	46562	0	0
T28	50862	0	0	0
T35	0	64931	0	0
T42	21363	0	0	0
T64	20259	0	0	0
T68	17651	0	0	0
T121	10532	0	0	0
T252	0	92859	0	0
T287	0	68076	0	0
T288	0	142645	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	3050	0	0
T15	637111	0	0	0
T20	240655	61	0	0
T22	0	57	0	0
T35	412246	74	0	0
T137	52721	0	0	0
T138	81315	0	0	0
T154	14189	0	0	0
T214	30612	0	0	0
T227	14132	0	0	0
T252	0	32	0	0
T270	0	94	0	0
T272	0	118	0	0
T289	0	53	0	0
T341	0	101	0	0
T342	0	146	0	0
T343	0	147	0	0
T344	31430	0	0	0
T345	30711	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	2651	0	0
T15	637111	0	0	0
T20	240655	27	0	0
T22	0	47	0	0
T35	412246	83	0	0
T137	52721	0	0	0
T138	81315	0	0	0
T154	14189	0	0	0
T214	30612	0	0	0
T227	14132	0	0	0
T252	0	89	0	0
T270	0	86	0	0
T272	0	198	0	0
T289	0	49	0	0
T341	0	63	0	0
T342	0	197	0	0
T343	0	118	0	0
T344	31430	0	0	0
T345	30711	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	3071	0	0
T15	637111	0	0	0
T20	240655	61	0	0
T22	0	76	0	0
T35	412246	75	0	0
T137	52721	0	0	0
T138	81315	0	0	0
T154	14189	0	0	0
T214	30612	0	0	0
T227	14132	0	0	0
T252	0	85	0	0
T270	0	71	0	0
T272	0	171	0	0
T289	0	44	0	0
T341	0	143	0	0
T342	0	117	0	0
T343	0	107	0	0
T344	31430	0	0	0
T345	30711	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	3131	0	0
T15	637111	0	0	0
T20	240655	62	0	0
T22	0	51	0	0
T35	412246	90	0	0
T137	52721	0	0	0
T138	81315	0	0	0
T154	14189	0	0	0
T214	30612	0	0	0
T227	14132	0	0	0
T252	0	68	0	0
T270	0	86	0	0
T272	0	165	0	0
T289	0	43	0	0
T341	0	100	0	0
T342	0	159	0	0
T343	0	163	0	0
T344	31430	0	0	0
T345	30711	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	2954	0	0
T15	637111	0	0	0
T20	240655	72	0	0
T22	0	29	0	0
T35	412246	61	0	0
T137	52721	0	0	0
T138	81315	0	0	0
T154	14189	0	0	0
T214	30612	0	0	0
T227	14132	0	0	0
T252	0	88	0	0
T270	0	139	0	0
T272	0	183	0	0
T289	0	51	0	0
T341	0	127	0	0
T342	0	158	0	0
T343	0	69	0	0
T344	31430	0	0	0
T345	30711	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	2027	0	0
T15	637111	0	0	0
T20	240655	85	0	0
T22	0	47	0	0
T35	412246	94	0	0
T137	52721	0	0	0
T138	81315	0	0	0
T154	14189	0	0	0
T214	30612	0	0	0
T227	14132	0	0	0
T252	0	47	0	0
T270	0	118	0	0
T272	0	219	0	0
T289	0	39	0	0
T341	0	103	0	0
T342	0	75	0	0
T343	0	140	0	0
T344	31430	0	0	0
T345	30711	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	1314	0	0
T15	637111	0	0	0
T20	240655	51	0	0
T22	0	18	0	0
T35	412246	54	0	0
T137	52721	0	0	0
T138	81315	0	0	0
T154	14189	0	0	0
T214	30612	0	0	0
T227	14132	0	0	0
T252	0	21	0	0
T270	0	46	0	0
T272	0	99	0	0
T289	0	38	0	0
T341	0	49	0	0
T342	0	88	0	0
T343	0	99	0	0
T344	31430	0	0	0
T345	30711	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	1509	0	0
T15	637111	0	0	0
T20	240655	34	0	0
T22	0	26	0	0
T35	412246	73	0	0
T137	52721	0	0	0
T138	81315	0	0	0
T154	14189	0	0	0
T214	30612	0	0	0
T227	14132	0	0	0
T252	0	43	0	0
T270	0	76	0	0
T272	0	124	0	0
T289	0	15	0	0
T341	0	74	0	0
T342	0	129	0	0
T343	0	102	0	0
T344	31430	0	0	0
T345	30711	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	3026	0	0
T15	637111	0	0	0
T20	240655	25	0	0
T22	0	40	0	0
T35	412246	101	0	0
T137	52721	0	0	0
T138	81315	0	0	0
T154	14189	0	0	0
T214	30612	0	0	0
T227	14132	0	0	0
T252	0	80	0	0
T270	0	82	0	0
T272	0	182	0	0
T289	0	38	0	0
T341	0	118	0	0
T342	0	156	0	0
T343	0	119	0	0
T344	31430	0	0	0
T345	30711	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	3512	0	0
T15	637111	0	0	0
T20	240655	52	0	0
T22	0	19	0	0
T35	412246	111	0	0
T137	52721	0	0	0
T138	81315	0	0	0
T143	0	27	0	0
T154	14189	0	0	0
T214	30612	0	0	0
T227	14132	0	0	0
T252	0	54	0	0
T272	0	143	0	0
T289	0	47	0	0
T341	0	97	0	0
T344	31430	0	0	0
T345	30711	0	0	0
T346	0	27	0	0
T347	0	77	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	2798	0	0
T15	637111	0	0	0
T20	240655	27	0	0
T22	0	69	0	0
T35	412246	90	0	0
T137	52721	0	0	0
T138	81315	0	0	0
T154	14189	0	0	0
T214	30612	0	0	0
T227	14132	0	0	0
T252	0	59	0	0
T270	0	99	0	0
T272	0	180	0	0
T289	0	51	0	0
T341	0	87	0	0
T342	0	140	0	0
T343	0	91	0	0
T344	31430	0	0	0
T345	30711	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	2884	0	0
T15	637111	0	0	0
T20	240655	59	0	0
T22	0	42	0	0
T35	412246	90	0	0
T137	52721	0	0	0
T138	81315	0	0	0
T154	14189	0	0	0
T214	30612	0	0	0
T227	14132	0	0	0
T252	0	60	0	0
T270	0	85	0	0
T272	0	150	0	0
T289	0	24	0	0
T341	0	96	0	0
T342	0	130	0	0
T343	0	115	0	0
T344	31430	0	0	0
T345	30711	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	2708	0	0
T15	637111	0	0	0
T20	240655	70	0	0
T22	0	39	0	0
T35	412246	77	0	0
T137	52721	0	0	0
T138	81315	0	0	0
T154	14189	0	0	0
T214	30612	0	0	0
T227	14132	0	0	0
T252	0	54	0	0
T270	0	77	0	0
T272	0	113	0	0
T289	0	51	0	0
T341	0	111	0	0
T342	0	110	0	0
T343	0	128	0	0
T344	31430	0	0	0
T345	30711	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440337468	2762	0	0
T15	637111	0	0	0
T20	240655	44	0	0
T22	0	67	0	0
T35	412246	108	0	0
T137	52721	0	0	0
T138	81315	0	0	0
T154	14189	0	0	0
T214	30612	0	0	0
T227	14132	0	0	0
T252	0	27	0	0
T270	0	118	0	0
T272	0	148	0	0
T289	0	65	0	0
T341	0	127	0	0
T342	0	174	0	0
T343	0	130	0	0
T344	31430	0	0	0
T345	30711	0	0	0