SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
83.33 | 69.44 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
buf_err_code_cg_wrap[OtpSecret0ErrIdx] | 0.00 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpHwCfg0ErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpHwCfg1ErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
0.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 6 | 0 | 0.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 6 | 0 | 0.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 6 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
fsm_err | 0 | 1 | 1 | |
check_fail | 0 | 1 | 1 | |
ecc_uncorr_err | 0 | 1 | 1 | |
ecc_corr_err | 0 | 1 | 1 | |
macro_err | 0 | 1 | 1 | |
no_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 126633 | 1 | T1 | 215 | T4 | 231 | T5 | 1436 | ||||
check_fail | 4 | 1 | T65 | 1 | T66 | 1 | T67 | 1 | ||||
ecc_uncorr_err | 130 | 1 | T63 | 5 | T37 | 54 | T125 | 1 | ||||
ecc_corr_err | 334 | 1 | T63 | 9 | T64 | 53 | T36 | 69 | ||||
no_err | 162821 | 1 | T1 | 103 | T2 | 12 | T3 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 126763 | 1 | T1 | 215 | T4 | 231 | T5 | 1436 | ||||
check_fail | 2 | 1 | T39 | 1 | T40 | 1 | - | - | ||||
ecc_uncorr_err | 10 | 1 | T80 | 1 | T21 | 1 | T81 | 1 | ||||
ecc_corr_err | 302 | 1 | T36 | 62 | T37 | 48 | T38 | 67 | ||||
no_err | 162762 | 1 | T1 | 103 | T2 | 12 | T3 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 126657 | 1 | T1 | 215 | T4 | 231 | T5 | 1436 | ||||
check_fail | 10 | 1 | T28 | 1 | T29 | 1 | T30 | 1 | ||||
ecc_uncorr_err | 105 | 1 | T83 | 1 | T70 | 3 | T42 | 1 | ||||
ecc_corr_err | 190 | 1 | T25 | 47 | T26 | 51 | T27 | 51 | ||||
no_err | 163237 | 1 | T1 | 103 | T2 | 12 | T3 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 126573 | 1 | T1 | 215 | T4 | 231 | T5 | 1436 | ||||
check_fail | 32 | 1 | T47 | 1 | T48 | 1 | T49 | 1 | ||||
ecc_uncorr_err | 152 | 1 | T82 | 1 | T84 | 1 | T111 | 1 | ||||
ecc_corr_err | 108 | 1 | T44 | 23 | T45 | 68 | T46 | 17 | ||||
no_err | 163228 | 1 | T1 | 103 | T2 | 12 | T3 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 126481 | 1 | T1 | 215 | T4 | 231 | T5 | 1436 | ||||
check_fail | 19 | 1 | T8 | 1 | T57 | 1 | T58 | 1 | ||||
ecc_uncorr_err | 253 | 1 | T69 | 137 | T64 | 48 | T23 | 1 | ||||
ecc_corr_err | 121 | 1 | T54 | 48 | T55 | 71 | T56 | 2 | ||||
no_err | 163132 | 1 | T1 | 103 | T2 | 12 | T3 | 13 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |