Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7524178	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7377327

1

T1

2968

T2

118

T3

129

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8772183	1			T1	5168		T2	641		T3	496
values[0x0]	2341044	1			T1	475		T2	18		T3	21
values[0x1]	3788278	1			T1	496		T2	19		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4906833	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9994672

1

T1

3628

T2

276

T3

243

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51662	1			T4	290		T7	470		T9	4
valid_sources[0x01]	49946	1			T4	335		T7	496		T9	1
valid_sources[0x02]	51919	1			T4	316		T7	456		T9	5
valid_sources[0x03]	53511	1			T4	307		T7	500		T9	3
valid_sources[0x04]	61344	1			T4	347		T7	478		T9	5
valid_sources[0x05]	51740	1			T4	327		T7	430		T9	2
valid_sources[0x06]	51876	1			T4	350		T7	448		T9	5
valid_sources[0x07]	60320	1			T4	415		T7	505		T10	58
valid_sources[0x08]	48155	1			T4	311		T7	437		T9	1
valid_sources[0x09]	50683	1			T4	407		T7	477		T9	2
valid_sources[0x0a]	52052	1			T4	314		T7	475		T9	1
valid_sources[0x0b]	52774	1			T4	273		T7	454		T9	4
valid_sources[0x0c]	53298	1			T4	303		T7	479		T9	3
valid_sources[0x0d]	48989	1			T4	301		T7	539		T10	30
valid_sources[0x0e]	54185	1			T4	328		T7	521		T9	1
valid_sources[0x0f]	50944	1			T4	334		T7	473		T9	1
valid_sources[0x10]	52265	1			T4	348		T7	472		T9	4
valid_sources[0x11]	51434	1			T4	298		T7	431		T9	6
valid_sources[0x12]	52123	1			T4	364		T7	473		T9	2
valid_sources[0x13]	61454	1			T4	313		T7	479		T9	3
valid_sources[0x14]	50184	1			T4	392		T7	440		T9	6
valid_sources[0x15]	50834	1			T4	392		T7	538		T9	5
valid_sources[0x16]	57644	1			T4	340		T7	423		T9	5
valid_sources[0x17]	53208	1			T4	307		T7	474		T9	6
valid_sources[0x18]	54231	1			T4	354		T7	465		T9	3
valid_sources[0x19]	57814	1			T4	379		T7	475		T9	3
valid_sources[0x1a]	49801	1			T4	355		T7	451		T9	4
valid_sources[0x1b]	52047	1			T4	379		T7	458		T9	1
valid_sources[0x1c]	51514	1			T4	342		T7	440		T9	5
valid_sources[0x1d]	112132	1			T4	355		T5	58846		T7	477
valid_sources[0x1e]	49526	1			T4	351		T7	493		T9	6
valid_sources[0x1f]	52779	1			T4	383		T7	450		T9	1
valid_sources[0x20]	49201	1			T4	349		T7	460		T9	7
valid_sources[0x21]	95403	1			T4	364		T7	467		T9	3
valid_sources[0x22]	59122	1			T4	383		T7	446		T9	6
valid_sources[0x23]	49854	1			T4	300		T7	455		T9	5
valid_sources[0x24]	64583	1			T4	414		T7	458		T9	6
valid_sources[0x25]	50222	1			T4	361		T7	485		T9	6
valid_sources[0x26]	58037	1			T4	353		T7	429		T9	1
valid_sources[0x27]	70039	1			T4	370		T7	446		T9	4
valid_sources[0x28]	51850	1			T4	355		T7	465		T9	6
valid_sources[0x29]	165139	1			T4	329		T7	458		T9	2
valid_sources[0x2a]	51659	1			T4	335		T7	456		T9	1
valid_sources[0x2b]	50708	1			T4	320		T7	483		T9	3
valid_sources[0x2c]	53055	1			T4	307		T7	480		T9	2
valid_sources[0x2d]	50885	1			T4	356		T7	481		T9	5
valid_sources[0x2e]	51000	1			T4	365		T7	476		T9	2
valid_sources[0x2f]	50375	1			T4	374		T7	498		T9	1
valid_sources[0x30]	49972	1			T4	357		T7	497		T9	3
valid_sources[0x31]	60990	1			T4	324		T7	457		T9	3
valid_sources[0x32]	67484	1			T4	348		T7	469		T9	1
valid_sources[0x33]	54085	1			T4	406		T7	465		T9	1
valid_sources[0x34]	54616	1			T4	392		T7	462		T9	7
valid_sources[0x35]	78322	1			T4	295		T7	461		T9	1
valid_sources[0x36]	49902	1			T4	271		T7	473		T9	8
valid_sources[0x37]	65489	1			T4	318		T7	421		T10	33
valid_sources[0x38]	64873	1			T4	352		T7	473		T9	4
valid_sources[0x39]	62809	1			T4	333		T7	483		T9	5
valid_sources[0x3a]	64001	1			T4	364		T7	403		T9	2
valid_sources[0x3b]	50779	1			T4	356		T7	472		T9	3
valid_sources[0x3c]	51549	1			T4	300		T7	485		T9	3
valid_sources[0x3d]	49704	1			T4	384		T7	431		T9	2
valid_sources[0x3e]	59900	1			T4	302		T7	461		T9	4
valid_sources[0x3f]	52288	1			T4	346		T7	487		T9	2
valid_sources[0x40]	53539	1			T4	344		T7	446		T9	3
valid_sources[0x41]	48279	1			T4	324		T7	475		T10	50
valid_sources[0x42]	53775	1			T4	355		T7	438		T9	2
valid_sources[0x43]	48980	1			T4	383		T7	468		T9	1
valid_sources[0x44]	55541	1			T4	328		T7	445		T9	4
valid_sources[0x45]	50488	1			T4	347		T7	469		T9	3
valid_sources[0x46]	51054	1			T4	325		T7	446		T9	7
valid_sources[0x47]	54372	1			T4	334		T7	523		T9	5
valid_sources[0x48]	60249	1			T4	362		T7	467		T9	3
valid_sources[0x49]	51269	1			T4	364		T7	493		T9	2
valid_sources[0x4a]	57215	1			T4	310		T7	469		T9	5
valid_sources[0x4b]	51263	1			T4	313		T7	446		T9	2
valid_sources[0x4c]	52228	1			T4	293		T7	473		T9	4
valid_sources[0x4d]	51110	1			T4	307		T7	462		T9	3
valid_sources[0x4e]	49372	1			T4	387		T7	451		T9	4
valid_sources[0x4f]	62617	1			T4	387		T7	482		T9	4
valid_sources[0x50]	56427	1			T4	298		T7	499		T9	1
valid_sources[0x51]	52804	1			T4	415		T7	405		T9	4
valid_sources[0x52]	103193	1			T4	368		T7	493		T9	2
valid_sources[0x53]	51278	1			T4	346		T7	465		T9	4
valid_sources[0x54]	51214	1			T4	272		T7	456		T9	2
valid_sources[0x55]	103499	1			T4	296		T7	506		T9	5
valid_sources[0x56]	59617	1			T4	366		T7	466		T9	3
valid_sources[0x57]	55650	1			T4	346		T7	484		T10	30
valid_sources[0x58]	50550	1			T4	367		T7	478		T9	1
valid_sources[0x59]	54397	1			T4	345		T7	455		T9	4
valid_sources[0x5a]	48918	1			T4	349		T7	476		T9	5
valid_sources[0x5b]	129466	1			T4	360		T7	513		T9	5
valid_sources[0x5c]	57190	1			T4	387		T7	478		T8	1831
valid_sources[0x5d]	49902	1			T4	349		T7	422		T9	6
valid_sources[0x5e]	57918	1			T4	297		T7	482		T9	1
valid_sources[0x5f]	55160	1			T4	348		T7	428		T9	3
valid_sources[0x60]	53737	1			T4	330		T7	469		T9	6
valid_sources[0x61]	57689	1			T4	328		T7	405		T10	35
valid_sources[0x62]	50160	1			T4	349		T7	458		T9	5
valid_sources[0x63]	50660	1			T4	371		T7	510		T9	3
valid_sources[0x64]	51228	1			T4	370		T7	465		T9	2
valid_sources[0x65]	56241	1			T4	385		T7	449		T9	1
valid_sources[0x66]	49808	1			T4	303		T7	497		T9	5
valid_sources[0x67]	55296	1			T4	358		T7	424		T9	3
valid_sources[0x68]	53753	1			T4	395		T7	477		T9	3
valid_sources[0x69]	49888	1			T4	343		T7	473		T9	2
valid_sources[0x6a]	53586	1			T4	324		T7	462		T9	1
valid_sources[0x6b]	65843	1			T4	350		T7	485		T9	1
valid_sources[0x6c]	50761	1			T4	311		T7	470		T9	4
valid_sources[0x6d]	55712	1			T4	359		T7	450		T9	1
valid_sources[0x6e]	58467	1			T4	334		T7	423		T9	2
valid_sources[0x6f]	52864	1			T4	368		T7	431		T9	1
valid_sources[0x70]	52372	1			T4	375		T7	425		T9	4
valid_sources[0x71]	94651	1			T4	326		T7	434		T9	6
valid_sources[0x72]	57178	1			T4	355		T7	458		T9	2
valid_sources[0x73]	50377	1			T4	384		T7	542		T9	3
valid_sources[0x74]	52781	1			T4	335		T7	494		T9	2
valid_sources[0x75]	54637	1			T4	281		T7	426		T9	2
valid_sources[0x76]	60172	1			T4	318		T7	445		T9	4
valid_sources[0x77]	53854	1			T4	390		T7	449		T9	4
valid_sources[0x78]	54032	1			T4	362		T7	447		T9	3
valid_sources[0x79]	61347	1			T4	375		T7	499		T9	4
valid_sources[0x7a]	89392	1			T4	311		T7	461		T9	4
valid_sources[0x7b]	70793	1			T4	378		T7	447		T9	6
valid_sources[0x7c]	52378	1			T4	385		T7	501		T9	1
valid_sources[0x7d]	62976	1			T4	370		T7	482		T9	3
valid_sources[0x7e]	48889	1			T4	332		T7	453		T9	3
valid_sources[0x7f]	52082	1			T4	349		T7	441		T9	2
valid_sources[0x80]	53752	1			T4	334		T7	466		T9	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3595610

1

T1

2486

T2

110

T3

112

values[0x0]

all_enables

biggest_size

1931566

1

T1

251

T2

7

T3

10

values[0x1]

all_enables

biggest_size

1850151

1

T1

231

T2

1

T3

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	251890	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8964450

1

T1

20

T2

20

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2294961	1			T1	10		T2	10		T3	10
values[0x0]	3360745	1			T1	4		T2	5		T3	5
values[0x1]	3560634	1			T1	6		T2	5		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	90877	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9125463

1

T1

20

T2

20

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	34857	1			T4	255		T7	445		T177	2
valid_sources[0x01]	37270	1			T4	33		T7	413		T10	12
valid_sources[0x02]	36795	1			T4	435		T7	416		T10	4
valid_sources[0x03]	35489	1			T4	128		T7	423		T10	9
valid_sources[0x04]	36249	1			T7	417		T171	1		T11	191
valid_sources[0x05]	35922	1			T4	350		T7	416		T11	216
valid_sources[0x06]	34685	1			T4	54		T7	400		T177	1
valid_sources[0x07]	35135	1			T4	257		T7	377		T11	235
valid_sources[0x08]	36012	1			T4	620		T7	461		T171	1
valid_sources[0x09]	35785	1			T4	372		T7	393		T11	206
valid_sources[0x0a]	35971	1			T4	203		T7	432		T96	1
valid_sources[0x0b]	35761	1			T4	914		T7	405		T171	1
valid_sources[0x0c]	34451	1			T4	70		T7	438		T11	283
valid_sources[0x0d]	35331	1			T4	344		T7	430		T177	1
valid_sources[0x0e]	35461	1			T4	203		T7	408		T25	4
valid_sources[0x0f]	36234	1			T4	382		T7	415		T177	1
valid_sources[0x10]	34582	1			T4	267		T7	440		T177	1
valid_sources[0x11]	35321	1			T4	254		T7	424		T177	1
valid_sources[0x12]	34686	1			T4	1048		T7	408		T177	1
valid_sources[0x13]	35347	1			T1	1		T4	904		T7	409
valid_sources[0x14]	35498	1			T4	339		T7	377		T177	1
valid_sources[0x15]	34821	1			T4	135		T7	398		T177	1
valid_sources[0x16]	37205	1			T4	82		T7	409		T96	2
valid_sources[0x17]	36508	1			T4	33		T7	417		T11	167
valid_sources[0x18]	35844	1			T2	5		T4	461		T7	413
valid_sources[0x19]	35258	1			T4	100		T7	403		T96	2
valid_sources[0x1a]	36597	1			T4	4		T7	409		T10	4
valid_sources[0x1b]	36370	1			T4	410		T7	401		T10	1
valid_sources[0x1c]	36141	1			T4	432		T7	442		T11	288
valid_sources[0x1d]	36847	1			T4	409		T7	450		T11	154
valid_sources[0x1e]	35858	1			T4	76		T7	407		T171	1
valid_sources[0x1f]	34963	1			T4	4		T7	423		T171	1
valid_sources[0x20]	35119	1			T4	75		T7	429		T177	1
valid_sources[0x21]	36837	1			T1	1		T4	255		T7	431
valid_sources[0x22]	36965	1			T4	292		T7	397		T11	572
valid_sources[0x23]	36371	1			T1	2		T4	621		T7	369
valid_sources[0x24]	34008	1			T4	20		T7	401		T96	1
valid_sources[0x25]	35505	1			T4	101		T7	426		T10	2
valid_sources[0x26]	34602	1			T1	1		T4	276		T7	420
valid_sources[0x27]	36329	1			T4	645		T7	464		T25	2
valid_sources[0x28]	35173	1			T3	1		T4	451		T7	436
valid_sources[0x29]	35047	1			T4	458		T7	408		T177	1
valid_sources[0x2a]	38266	1			T1	1		T2	7		T4	2138
valid_sources[0x2b]	35448	1			T4	207		T7	479		T171	1
valid_sources[0x2c]	36589	1			T4	512		T7	422		T11	247
valid_sources[0x2d]	35166	1			T4	310		T7	417		T10	6
valid_sources[0x2e]	35707	1			T2	1		T4	1325		T7	373
valid_sources[0x2f]	35310	1			T4	374		T6	8		T7	417
valid_sources[0x30]	37519	1			T4	380		T7	396		T171	2
valid_sources[0x31]	36534	1			T4	34		T7	398		T11	150
valid_sources[0x32]	35126	1			T4	217		T7	412		T11	288
valid_sources[0x33]	37883	1			T4	125		T7	403		T93	3
valid_sources[0x34]	35656	1			T1	1		T4	519		T7	421
valid_sources[0x35]	35676	1			T1	1		T4	181		T7	432
valid_sources[0x36]	35490	1			T1	1		T4	128		T7	408
valid_sources[0x37]	35251	1			T7	454		T11	172		T172	1
valid_sources[0x38]	35811	1			T4	352		T7	407		T171	1
valid_sources[0x39]	33669	1			T3	1		T4	259		T7	443
valid_sources[0x3a]	36247	1			T4	341		T7	409		T177	2
valid_sources[0x3b]	38698	1			T4	680		T7	425		T177	3
valid_sources[0x3c]	36886	1			T4	671		T7	426		T171	1
valid_sources[0x3d]	35729	1			T4	431		T7	435		T11	272
valid_sources[0x3e]	35369	1			T4	90		T7	438		T171	1
valid_sources[0x3f]	34914	1			T4	170		T7	431		T11	178
valid_sources[0x40]	39216	1			T4	40		T7	469		T10	2
valid_sources[0x41]	38454	1			T4	972		T7	431		T171	2
valid_sources[0x42]	36547	1			T7	415		T11	248		T172	4
valid_sources[0x43]	34730	1			T4	453		T7	441		T11	362
valid_sources[0x44]	35712	1			T4	124		T7	393		T11	193
valid_sources[0x45]	36723	1			T4	608		T7	394		T11	416
valid_sources[0x46]	34644	1			T4	131		T7	407		T95	20
valid_sources[0x47]	37665	1			T4	2		T7	383		T96	1
valid_sources[0x48]	34667	1			T4	42		T7	430		T10	1
valid_sources[0x49]	35669	1			T4	121		T7	430		T96	1
valid_sources[0x4a]	36571	1			T7	407		T177	1		T11	172
valid_sources[0x4b]	35652	1			T4	57		T7	389		T11	414
valid_sources[0x4c]	35005	1			T4	297		T7	424		T171	1
valid_sources[0x4d]	36282	1			T4	88		T5	540		T7	428
valid_sources[0x4e]	35885	1			T4	324		T7	421		T96	1
valid_sources[0x4f]	36760	1			T3	7		T4	134		T7	381
valid_sources[0x50]	36983	1			T4	7		T7	412		T96	3
valid_sources[0x51]	36500	1			T4	210		T7	401		T177	2
valid_sources[0x52]	37040	1			T4	75		T7	420		T11	222
valid_sources[0x53]	36603	1			T4	103		T7	450		T177	1
valid_sources[0x54]	38339	1			T4	437		T7	435		T177	1
valid_sources[0x55]	35529	1			T4	257		T7	443		T25	1
valid_sources[0x56]	37007	1			T4	160		T7	435		T11	191
valid_sources[0x57]	36346	1			T4	798		T7	394		T25	4
valid_sources[0x58]	36113	1			T4	466		T7	457		T96	3
valid_sources[0x59]	35930	1			T4	304		T7	445		T10	1
valid_sources[0x5a]	34549	1			T4	237		T7	402		T177	2
valid_sources[0x5b]	35116	1			T3	2		T4	114		T7	418
valid_sources[0x5c]	37663	1			T4	982		T7	394		T96	1
valid_sources[0x5d]	36163	1			T4	188		T7	394		T93	1
valid_sources[0x5e]	36374	1			T4	97		T7	436		T10	7
valid_sources[0x5f]	35973	1			T4	682		T7	411		T177	2
valid_sources[0x60]	38019	1			T4	562		T7	412		T171	1
valid_sources[0x61]	35403	1			T4	224		T7	408		T96	4
valid_sources[0x62]	36968	1			T4	491		T7	454		T177	5
valid_sources[0x63]	36136	1			T4	23		T7	385		T177	2
valid_sources[0x64]	35234	1			T4	144		T7	439		T25	1
valid_sources[0x65]	36507	1			T4	163		T7	445		T177	1
valid_sources[0x66]	36023	1			T4	480		T7	477		T96	1
valid_sources[0x67]	34796	1			T4	15		T7	406		T96	2
valid_sources[0x68]	36374	1			T4	606		T7	429		T11	158
valid_sources[0x69]	35628	1			T4	71		T7	433		T96	1
valid_sources[0x6a]	36177	1			T4	155		T7	414		T96	4
valid_sources[0x6b]	38116	1			T7	449		T171	1		T11	83
valid_sources[0x6c]	35461	1			T4	286		T7	409		T96	1
valid_sources[0x6d]	35749	1			T4	223		T7	422		T11	372
valid_sources[0x6e]	34995	1			T1	1		T4	133		T7	434
valid_sources[0x6f]	37479	1			T4	1089		T7	398		T10	1
valid_sources[0x70]	35116	1			T4	649		T7	429		T171	2
valid_sources[0x71]	34987	1			T4	383		T7	420		T11	295
valid_sources[0x72]	35481	1			T4	90		T7	393		T11	313
valid_sources[0x73]	34666	1			T4	84		T7	414		T171	1
valid_sources[0x74]	34484	1			T7	423		T171	2		T11	170
valid_sources[0x75]	37095	1			T4	586		T7	440		T177	2
valid_sources[0x76]	35517	1			T4	405		T7	409		T177	1
valid_sources[0x77]	33561	1			T4	154		T7	419		T25	12
valid_sources[0x78]	34784	1			T4	266		T7	418		T177	2
valid_sources[0x79]	34486	1			T4	251		T7	453		T177	1
valid_sources[0x7a]	35724	1			T3	2		T4	12		T7	398
valid_sources[0x7b]	34699	1			T4	263		T7	367		T10	2
valid_sources[0x7c]	34720	1			T4	597		T7	401		T177	1
valid_sources[0x7d]	35445	1			T4	472		T7	392		T200	40
valid_sources[0x7e]	35086	1			T7	429		T11	377		T172	1
valid_sources[0x7f]	35780	1			T4	964		T7	401		T171	1
valid_sources[0x80]	35656	1			T4	1683		T7	408		T11	220

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2281106

1

T1

10

T2

10

T3

10

values[0x0]

all_enables

biggest_size

3343593

1

T1

4

T2

5

T3

5

values[0x1]

all_enables

biggest_size

3339751

1

T1

6

T2

5

T3

5