Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25551347

1

T1

3171

T2

560

T3

410

full_word

8468056

1

T1

2968

T2

118

T3

129

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34019093	1			T1	6139		T2	678		T3	539
auto[TlIntgErrCmd]	106	1			T258	9		T259	9		T260	2
auto[TlIntgErrData]	111	1			T258	3		T259	8		T260	3
auto[TlIntgErrBoth]	93	1			T258	8		T259	3		T260	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10099314

1

T1

5168

T2

641

T3

496

auto[1]

23920089

1

T1

971

T2

37

T3

43

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6369903	1			T1	2682		T2	531		T3	384
auto[TlIntgErrNone]	partial	auto[1]	19181149	1			T1	489		T2	29		T3	26
auto[TlIntgErrNone]	full_word	auto[0]	3729272	1			T1	2486		T2	110		T3	112
auto[TlIntgErrNone]	full_word	auto[1]	4738769	1			T1	482		T2	8		T3	17
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T258	5		T259	2		T352	4
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T258	4		T259	6		T260	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T353	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T259	1		T357	1		T359	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T258	1		T259	7		T260	3
auto[TlIntgErrData]	partial	auto[1]	49	1			T258	2		T259	1		T352	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T352	1		T357	1		T359	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T356	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T258	2		T259	2		T260	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T258	5		T259	1		T260	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T258	1		T260	1		T360	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T361	1		-	-		-	-