Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.20		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	488193335	8128441	0	0
check_regwen_rd_A	488193335	3358	0	0
check_timeout_rd_A	488193335	2815	0	0
check_trigger_regwen_rd_A	488193335	3407	0	0
consistency_check_period_rd_A	488193335	3582	0	0
creator_sw_cfg_read_lock_rd_A	488193335	3007	0	0
direct_access_address_rd_A	488193335	1926	0	0
direct_access_wdata_0_rd_A	488193335	1357	0	0
direct_access_wdata_1_rd_A	488193335	1635	0	0
integrity_check_period_rd_A	488193335	3338	0	0
intr_enable_rd_A	488193335	4313	0	0
owner_sw_cfg_read_lock_rd_A	488193335	2800	0	0
rot_creator_auth_codesign_read_lock_rd_A	488193335	3132	0	0
rot_creator_auth_state_read_lock_rd_A	488193335	2730	0	0
vendor_test_read_lock_rd_A	488193335	2715	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	8128441	0	0
T4	589526	72689	0	0
T5	823606	0	0	0
T6	13210	0	0	0
T7	551165	92211	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T11	0	49711	0	0
T12	0	65221	0	0
T13	0	198728	0	0
T25	86084	0	0	0
T34	0	68946	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T134	0	37330	0	0
T243	0	34137	0	0
T252	0	59033	0	0
T267	0	13791	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	3358	0	0
T7	551165	167	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T15	0	43	0	0
T25	86084	0	0	0
T53	18980	0	0	0
T71	12686	0	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T94	3920	0	0	0
T134	0	13	0	0
T252	0	60	0	0
T267	0	19	0	0
T269	0	61	0	0
T279	0	36	0	0
T329	0	72	0	0
T330	0	31	0	0
T331	0	48	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	2815	0	0
T7	551165	142	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T15	0	46	0	0
T25	86084	0	0	0
T53	18980	0	0	0
T71	12686	0	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T94	3920	0	0	0
T134	0	37	0	0
T252	0	49	0	0
T267	0	11	0	0
T269	0	36	0	0
T279	0	50	0	0
T329	0	47	0	0
T330	0	28	0	0
T331	0	44	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	3407	0	0
T7	551165	123	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T15	0	24	0	0
T25	86084	0	0	0
T53	18980	0	0	0
T71	12686	0	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T94	3920	0	0	0
T134	0	31	0	0
T252	0	101	0	0
T267	0	13	0	0
T269	0	44	0	0
T279	0	50	0	0
T329	0	28	0	0
T330	0	52	0	0
T331	0	53	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	3582	0	0
T7	551165	130	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T15	0	27	0	0
T25	86084	0	0	0
T53	18980	0	0	0
T71	12686	0	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T94	3920	0	0	0
T134	0	10	0	0
T252	0	67	0	0
T267	0	17	0	0
T269	0	59	0	0
T279	0	69	0	0
T329	0	83	0	0
T330	0	37	0	0
T331	0	36	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	3007	0	0
T7	551165	146	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T15	0	42	0	0
T25	86084	0	0	0
T53	18980	0	0	0
T71	12686	0	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T94	3920	0	0	0
T134	0	27	0	0
T252	0	66	0	0
T267	0	24	0	0
T269	0	50	0	0
T279	0	28	0	0
T329	0	95	0	0
T330	0	66	0	0
T331	0	58	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	1926	0	0
T7	551165	114	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T15	0	32	0	0
T25	86084	0	0	0
T53	18980	0	0	0
T71	12686	0	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T94	3920	0	0	0
T134	0	9	0	0
T252	0	88	0	0
T267	0	21	0	0
T269	0	44	0	0
T279	0	61	0	0
T329	0	79	0	0
T330	0	48	0	0
T331	0	41	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	1357	0	0
T7	551165	61	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T15	0	22	0	0
T25	86084	0	0	0
T53	18980	0	0	0
T71	12686	0	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T94	3920	0	0	0
T134	0	17	0	0
T252	0	77	0	0
T267	0	8	0	0
T269	0	34	0	0
T279	0	37	0	0
T329	0	77	0	0
T330	0	32	0	0
T331	0	23	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	1635	0	0
T7	551165	113	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T15	0	33	0	0
T25	86084	0	0	0
T53	18980	0	0	0
T71	12686	0	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T94	3920	0	0	0
T134	0	11	0	0
T252	0	67	0	0
T267	0	17	0	0
T269	0	42	0	0
T279	0	29	0	0
T329	0	71	0	0
T330	0	84	0	0
T331	0	40	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	3338	0	0
T7	551165	93	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T15	0	41	0	0
T25	86084	0	0	0
T53	18980	0	0	0
T71	12686	0	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T94	3920	0	0	0
T134	0	30	0	0
T252	0	69	0	0
T267	0	11	0	0
T269	0	45	0	0
T279	0	39	0	0
T329	0	43	0	0
T330	0	26	0	0
T331	0	48	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	4313	0	0
T7	551165	114	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T15	0	35	0	0
T25	86084	0	0	0
T53	18980	0	0	0
T71	12686	0	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T94	3920	0	0	0
T123	0	25	0	0
T134	0	43	0	0
T252	0	83	0	0
T253	0	35	0	0
T267	0	14	0	0
T269	0	102	0	0
T329	0	31	0	0
T332	0	22	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	2800	0	0
T7	551165	109	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T15	0	53	0	0
T25	86084	0	0	0
T53	18980	0	0	0
T71	12686	0	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T94	3920	0	0	0
T134	0	18	0	0
T252	0	70	0	0
T267	0	35	0	0
T269	0	61	0	0
T279	0	38	0	0
T329	0	52	0	0
T330	0	35	0	0
T331	0	76	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	3132	0	0
T7	551165	168	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T15	0	40	0	0
T25	86084	0	0	0
T53	18980	0	0	0
T71	12686	0	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T94	3920	0	0	0
T134	0	31	0	0
T252	0	60	0	0
T267	0	15	0	0
T269	0	88	0	0
T279	0	29	0	0
T329	0	51	0	0
T330	0	46	0	0
T331	0	38	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	2730	0	0
T7	551165	101	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T15	0	50	0	0
T25	86084	0	0	0
T53	18980	0	0	0
T71	12686	0	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T94	3920	0	0	0
T134	0	25	0	0
T252	0	86	0	0
T267	0	12	0	0
T269	0	69	0	0
T279	0	61	0	0
T329	0	45	0	0
T330	0	37	0	0
T331	0	41	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488193335	2715	0	0
T7	551165	124	0	0
T8	15173	0	0	0
T9	18060	0	0	0
T10	63680	0	0	0
T15	0	40	0	0
T25	86084	0	0	0
T53	18980	0	0	0
T71	12686	0	0	0
T76	8996	0	0	0
T93	11845	0	0	0
T94	3920	0	0	0
T134	0	36	0	0
T252	0	91	0	0
T267	0	20	0	0
T269	0	49	0	0
T279	0	79	0	0
T329	0	63	0	0
T330	0	68	0	0
T331	0	43	0	0