Module Definition
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Module : prim_ram_1p_adv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.53 98.59 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.45 97.27 100.00 100.00 100.00 100.00 gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_mem 98.85 96.55 100.00 100.00
u_req_d_buf 100.00 100.00
u_write_d_buf 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_ram_1p_adv
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN12311100.00
ALWAYS12633100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN24800
CONT_ASSIGN24911100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25511100.00
ALWAYS28855100.00
ALWAYS29977100.00
ALWAYS33433100.00
ALWAYS34355100.00
CONT_ASSIGN35911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
102 1 1
103 1 1
123 1 1
126 1 1
127 1 1
129 1 1
133 1 1
134 1 1
135 1 1
136 1 1
137 1 1
138 1 1
147 1 1
156 1 1
248 unreachable
249 1 1
251 1 1
255 1 1
288 1 1
289 1 1
290 1 1
292 1 1
293 1 1
299 1 1
300 1 1
301 1 1
302 1 1
304 1 1
305 1 1
306 1 1
334 1 1
335 1 1
337 1 1
343 1 1
344 1 1
345 1 1
347 1 1
349 1 1
359 1 1


Branch Coverage for Module : prim_ram_1p_adv
Line No.TotalCoveredPercent
Branches 10 10 100.00
IF 126 2 2 100.00
IF 299 2 2 100.00
IF 288 2 2 100.00
IF 343 2 2 100.00
IF 334 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 126 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 299 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 288 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 343 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 334 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_ram_1p_adv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CannotHaveEccAndParity_A 1152 1152 0 0


CannotHaveEccAndParity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1152 1152 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%