Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_sync_reqack_data
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_edn_req.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 83.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 100.00 92.31 100.00 100.00 u_prim_edn_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 95.83 100.00 83.33 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Module : prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 485151582 520633 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 485151582 520575 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 485151582 520633 0 0
T1 73189 94 0 0
T2 18470 146 0 0
T3 17552 184 0 0
T4 589526 3482 0 0
T5 823606 2476 0 0
T6 13210 94 0 0
T7 551165 2144 0 0
T8 15173 0 0 0
T9 18060 0 0 0
T10 63680 750 0 0
T25 0 284 0 0
T95 0 192 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 485151582 520575 0 0
T1 73189 94 0 0
T2 18470 146 0 0
T3 17552 184 0 0
T4 589526 3482 0 0
T5 823606 2476 0 0
T6 13210 94 0 0
T7 551165 2144 0 0
T8 15173 0 0 0
T9 18060 0 0 0
T10 63680 750 0 0
T25 0 284 0 0
T95 0 192 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%