Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T98,T133 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T98,T133 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T98,T133 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T98,T133 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T98,T133 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T98,T133 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 5 | 83.33 |
ALWAYS | 56 | 3 | 3 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
64 |
1 |
1 |
100.00 |
IF |
56 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T2,T3 |
|
0 |
1 |
Excluded |
|
VC_COV_UNR |
0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 5 | 83.33 |
ALWAYS | 56 | 3 | 3 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
64 |
1 |
1 |
100.00 |
IF |
56 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T2,T3 |
|
0 |
1 |
Excluded |
|
VC_COV_UNR |
0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 5 | 83.33 |
ALWAYS | 56 | 3 | 3 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
64 |
1 |
1 |
100.00 |
IF |
56 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T2,T3 |
|
0 |
1 |
Excluded |
|
VC_COV_UNR |
0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 5 | 83.33 |
ALWAYS | 56 | 3 | 3 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
64 |
1 |
1 |
100.00 |
IF |
56 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T2,T3 |
|
0 |
1 |
Excluded |
|
VC_COV_UNR |
0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 5 | 83.33 |
ALWAYS | 56 | 3 | 3 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
64 |
1 |
1 |
100.00 |
IF |
56 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T2,T3 |
|
0 |
1 |
Excluded |
|
VC_COV_UNR |
0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 5 | 83.33 |
ALWAYS | 56 | 3 | 3 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
64 |
1 |
1 |
100.00 |
IF |
56 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T2,T3 |
|
0 |
1 |
Excluded |
|
VC_COV_UNR |
0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T98,T133,T134 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T98,T133,T134 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T98,T133,T134 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T98,T133,T134 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T98,T133,T134 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T98,T133,T134 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T98,T133,T134 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T98,T133,T134 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T98,T133,T134 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T98,T133,T134 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T98,T133,T134 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T98,T133,T134 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T98,T133 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T98,T133 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T98,T133 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T98,T133 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T98,T133 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T98,T133 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 5 | 83.33 |
ALWAYS | 56 | 3 | 3 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
64 |
1 |
1 |
100.00 |
IF |
56 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T2,T3 |
|
0 |
1 |
Excluded |
|
VC_COV_UNR |
0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 5 | 83.33 |
ALWAYS | 56 | 3 | 3 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
64 |
1 |
1 |
100.00 |
IF |
56 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T2,T3 |
|
0 |
1 |
Excluded |
|
VC_COV_UNR |
0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 5 | 83.33 |
ALWAYS | 56 | 3 | 3 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
64 |
1 |
1 |
100.00 |
IF |
56 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T2,T3 |
|
0 |
1 |
Excluded |
|
VC_COV_UNR |
0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 5 | 83.33 |
ALWAYS | 56 | 3 | 3 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
64 |
1 |
1 |
100.00 |
IF |
56 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T2,T3 |
|
0 |
1 |
Excluded |
|
VC_COV_UNR |
0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T98,T133 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T98,T133 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T98,T133 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T98,T134,T120 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T98,T134,T120 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T98,T134,T120 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T98,T134,T120 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T98,T134,T120 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T98,T134,T120 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T98,T134,T120 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T98,T134,T120 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T98,T134,T120 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T98,T134,T120 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T98,T134,T120 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T98,T134,T120 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 5 | 83.33 |
ALWAYS | 56 | 3 | 3 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
64 |
1 |
1 |
100.00 |
IF |
56 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T2,T3 |
|
0 |
1 |
Excluded |
|
VC_COV_UNR |
0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 5 | 83.33 |
ALWAYS | 56 | 3 | 3 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
64 |
1 |
1 |
100.00 |
IF |
56 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T2,T3 |
|
0 |
1 |
Excluded |
|
VC_COV_UNR |
0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 5 | 83.33 |
ALWAYS | 56 | 3 | 3 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
64 |
1 |
1 |
100.00 |
IF |
56 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T2,T3 |
|
0 |
1 |
Excluded |
|
VC_COV_UNR |
0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 5 | 83.33 |
ALWAYS | 56 | 3 | 3 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3
| Total | Covered | Percent |
Conditions | 1 | 1 | 100.00 |
Logical | 1 | 1 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
64 |
1 |
1 |
100.00 |
IF |
56 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T2,T3 |
|
0 |
1 |
Excluded |
|
VC_COV_UNR |
0 |
0 |
Covered |
T1,T2,T3 |
|