Unified Coverage Report :: Module :: prim_present

Module : prim_present

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc	100.00	100.00	100.00			100.00	100.00
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	91.67	100.00		100.00	100.00	100.00	u_otp_ctrl_scrmbl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	91.67	100.00		100.00	100.00	100.00	u_otp_ctrl_scrmbl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_present ( parameter DataWidth=64,KeyWidth=128,NumRounds=31,NumPhysRounds=1,Decrypt=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
63	1	1
64	1	1
69	1	1
106	1	1
109	1	1
111	1	1
123	1	1
139	1	1
144	1	1
145	1	1

---

Line Coverage for Module : prim_present ( parameter DataWidth=64,KeyWidth=128,NumRounds=31,NumPhysRounds=1,Decrypt=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
63	1	1
64	1	1
69	1	1
74	1	1
77	1	1
79	1	1
91	1	1
139	1	1
144	1	1
145	1	1

---

Cond Coverage for Module : prim_present

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION 
 Number  Term
      1  (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
                --------------1--------------

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_present

	Line No.	Total	Covered	Percent
Branches		1	1	100.00
TERNARY	139	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	((int'(idx_o) == LastRoundIdx)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

---

Assert Coverage for Module : prim_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SupportedNumPhysRounds0_A	2304	2304	0	0
SupportedNumPhysRounds1_A	2304	2304	0	0
SupportedNumRounds_A	2304	2304	0	0
SupportedWidths_A	2304	2304	0	0

SupportedNumPhysRounds0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2304	2304	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

SupportedNumPhysRounds1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2304	2304	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

SupportedNumRounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2304	2304	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

SupportedWidths_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2304	2304	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

Line Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
63	1	1
64	1	1
69	1	1
106	1	1
109	1	1
111	1	1
123	1	1
139	1	1
144	1	1
145	1	1

---

Cond Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION 
 Number  Term
      1  (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
                --------------1--------------

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc

	Line No.	Total	Covered	Percent
Branches		1	1	100.00
TERNARY	139	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	((int'(idx_o) == LastRoundIdx)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SupportedNumPhysRounds0_A	1152	1152	0	0
SupportedNumPhysRounds1_A	1152	1152	0	0
SupportedNumRounds_A	1152	1152	0	0
SupportedWidths_A	1152	1152	0	0

SupportedNumPhysRounds0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedNumPhysRounds1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedNumRounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedWidths_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
63	1	1
64	1	1
69	1	1
74	1	1
77	1	1
79	1	1
91	1	1
139	1	1
144	1	1
145	1	1

---

Cond Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION 
 Number  Term
      1  (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
                --------------1--------------

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec

	Line No.	Total	Covered	Percent
Branches		1	1	100.00
TERNARY	139	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	((int'(idx_o) == LastRoundIdx)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SupportedNumPhysRounds0_A	1152	1152	0	0
SupportedNumPhysRounds1_A	1152	1152	0	0
SupportedNumRounds_A	1152	1152	0	0
SupportedWidths_A	1152	1152	0	0

SupportedNumPhysRounds0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedNumPhysRounds1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedNumRounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedWidths_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0