Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

22994105

1

T1

4211

T2

2669

T3

304599

full_word

7644762

1

T1

921

T2

2146

T3

87974

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30638547	1			T1	5132		T2	4815		T3	392573
auto[TlIntgErrCmd]	111	1			T249	8		T250	4		T251	8
auto[TlIntgErrData]	107	1			T249	7		T250	4		T251	4
auto[TlIntgErrBoth]	102	1			T249	5		T250	2		T251	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9362856

1

T1

4835

T2

4327

T3

53250

auto[1]

21276011

1

T1

297

T2

488

T3

339323

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5947319	1			T1	4020		T2	2377		T3	29879
auto[TlIntgErrNone]	partial	auto[1]	17046497	1			T1	191		T2	292		T3	274720
auto[TlIntgErrNone]	full_word	auto[0]	3415379	1			T1	815		T2	1950		T3	23371
auto[TlIntgErrNone]	full_word	auto[1]	4229352	1			T1	106		T2	196		T3	64603
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T249	2		T250	1		T251	5
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T249	4		T250	3		T251	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T249	1		T255	1		T348	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T249	1		T255	2		T347	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T249	5		T250	3		T251	1
auto[TlIntgErrData]	partial	auto[1]	40	1			T249	1		T250	1		T251	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T249	1		T348	1		T343	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T344	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T250	1		T251	1		T347	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T249	5		T250	1		T251	6
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T251	1		T343	1		T349	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T255	1		T343	1		T349	1