Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	429060514	7180343	0	0
check_regwen_rd_A	429060514	3347	0	0
check_timeout_rd_A	429060514	2959	0	0
check_trigger_regwen_rd_A	429060514	3398	0	0
consistency_check_period_rd_A	429060514	3457	0	0
creator_sw_cfg_read_lock_rd_A	429060514	2737	0	0
direct_access_address_rd_A	429060514	2463	0	0
direct_access_wdata_0_rd_A	429060514	1697	0	0
direct_access_wdata_1_rd_A	429060514	2095	0	0
integrity_check_period_rd_A	429060514	3573	0	0
intr_enable_rd_A	429060514	4094	0	0
owner_sw_cfg_read_lock_rd_A	429060514	2620	0	0
rot_creator_auth_codesign_read_lock_rd_A	429060514	2921	0	0
rot_creator_auth_state_read_lock_rd_A	429060514	2827	0	0
vendor_test_read_lock_rd_A	429060514	2681	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	7180343	0	0
T3	392419	118944	0	0
T4	26035	0	0	0
T7	25215	0	0	0
T8	15883	0	0	0
T9	103550	0	0	0
T10	16277	0	0	0
T11	5702	0	0	0
T12	15038	0	0	0
T13	0	78778	0	0
T14	0	154743	0	0
T15	0	54666	0	0
T16	0	96727	0	0
T67	11449	0	0	0
T101	33407	0	0	0
T131	0	302299	0	0
T132	0	78536	0	0
T133	0	27791	0	0
T256	0	31500	0	0
T257	0	62266	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	3347	0	0
T16	843216	137	0	0
T18	0	200	0	0
T79	13829	0	0	0
T106	147083	0	0	0
T131	101717	0	0	0
T220	11859	0	0	0
T226	79624	0	0	0
T229	118548	0	0	0
T230	93221	0	0	0
T231	14079	0	0	0
T243	0	66	0	0
T244	0	89	0	0
T258	104369	0	0	0
T260	0	199	0	0
T312	0	103	0	0
T317	0	47	0	0
T318	0	39	0	0
T319	0	159	0	0
T320	0	140	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	2959	0	0
T16	843216	87	0	0
T18	0	225	0	0
T79	13829	0	0	0
T106	147083	0	0	0
T131	101717	0	0	0
T220	11859	0	0	0
T226	79624	0	0	0
T229	118548	0	0	0
T230	93221	0	0	0
T231	14079	0	0	0
T243	0	68	0	0
T244	0	97	0	0
T258	104369	0	0	0
T260	0	234	0	0
T312	0	140	0	0
T317	0	85	0	0
T318	0	35	0	0
T319	0	202	0	0
T320	0	172	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	3398	0	0
T16	843216	115	0	0
T18	0	191	0	0
T79	13829	0	0	0
T106	147083	0	0	0
T131	101717	0	0	0
T220	11859	0	0	0
T226	79624	0	0	0
T229	118548	0	0	0
T230	93221	0	0	0
T231	14079	0	0	0
T243	0	81	0	0
T244	0	67	0	0
T258	104369	0	0	0
T260	0	186	0	0
T312	0	96	0	0
T317	0	80	0	0
T318	0	52	0	0
T319	0	181	0	0
T320	0	89	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	3457	0	0
T16	843216	134	0	0
T18	0	211	0	0
T79	13829	0	0	0
T106	147083	0	0	0
T131	101717	0	0	0
T220	11859	0	0	0
T226	79624	0	0	0
T229	118548	0	0	0
T230	93221	0	0	0
T231	14079	0	0	0
T243	0	34	0	0
T244	0	108	0	0
T258	104369	0	0	0
T260	0	162	0	0
T312	0	98	0	0
T317	0	73	0	0
T318	0	69	0	0
T319	0	186	0	0
T320	0	151	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	2737	0	0
T16	843216	130	0	0
T18	0	174	0	0
T79	13829	0	0	0
T106	147083	0	0	0
T131	101717	0	0	0
T220	11859	0	0	0
T226	79624	0	0	0
T229	118548	0	0	0
T230	93221	0	0	0
T231	14079	0	0	0
T243	0	29	0	0
T244	0	80	0	0
T258	104369	0	0	0
T260	0	193	0	0
T312	0	142	0	0
T317	0	96	0	0
T318	0	31	0	0
T319	0	218	0	0
T320	0	139	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	2463	0	0
T16	843216	106	0	0
T18	0	229	0	0
T79	13829	0	0	0
T106	147083	0	0	0
T131	101717	0	0	0
T220	11859	0	0	0
T226	79624	0	0	0
T229	118548	0	0	0
T230	93221	0	0	0
T231	14079	0	0	0
T243	0	70	0	0
T244	0	80	0	0
T258	104369	0	0	0
T260	0	182	0	0
T312	0	114	0	0
T317	0	125	0	0
T318	0	40	0	0
T319	0	175	0	0
T320	0	160	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	1697	0	0
T16	843216	123	0	0
T18	0	153	0	0
T79	13829	0	0	0
T106	147083	0	0	0
T131	101717	0	0	0
T220	11859	0	0	0
T226	79624	0	0	0
T229	118548	0	0	0
T230	93221	0	0	0
T231	14079	0	0	0
T243	0	26	0	0
T244	0	30	0	0
T258	104369	0	0	0
T260	0	165	0	0
T312	0	111	0	0
T317	0	13	0	0
T318	0	19	0	0
T319	0	127	0	0
T320	0	172	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	2095	0	0
T16	843216	62	0	0
T18	0	149	0	0
T79	13829	0	0	0
T106	147083	0	0	0
T131	101717	0	0	0
T220	11859	0	0	0
T226	79624	0	0	0
T229	118548	0	0	0
T230	93221	0	0	0
T231	14079	0	0	0
T243	0	44	0	0
T244	0	74	0	0
T258	104369	0	0	0
T260	0	191	0	0
T312	0	130	0	0
T317	0	42	0	0
T318	0	36	0	0
T319	0	194	0	0
T320	0	172	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	3573	0	0
T16	843216	97	0	0
T18	0	177	0	0
T79	13829	0	0	0
T106	147083	0	0	0
T131	101717	0	0	0
T220	11859	0	0	0
T226	79624	0	0	0
T229	118548	0	0	0
T230	93221	0	0	0
T231	14079	0	0	0
T243	0	68	0	0
T244	0	87	0	0
T258	104369	0	0	0
T260	0	148	0	0
T312	0	104	0	0
T317	0	69	0	0
T318	0	40	0	0
T319	0	165	0	0
T320	0	225	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	4094	0	0
T6	484537	40	0	0
T13	350373	0	0	0
T16	0	149	0	0
T47	13638	0	0	0
T51	49241	0	0	0
T70	0	32	0	0
T74	10083	0	0	0
T88	17150	0	0	0
T89	78249	0	0	0
T90	15382	0	0	0
T91	26948	0	0	0
T92	146426	0	0	0
T121	0	15	0	0
T243	0	83	0	0
T244	0	62	0	0
T260	0	220	0	0
T284	0	26	0	0
T290	0	21	0	0
T317	0	50	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	2620	0	0
T16	843216	143	0	0
T18	0	160	0	0
T79	13829	0	0	0
T106	147083	0	0	0
T131	101717	0	0	0
T220	11859	0	0	0
T226	79624	0	0	0
T229	118548	0	0	0
T230	93221	0	0	0
T231	14079	0	0	0
T243	0	29	0	0
T244	0	76	0	0
T258	104369	0	0	0
T260	0	214	0	0
T312	0	126	0	0
T317	0	81	0	0
T318	0	27	0	0
T319	0	143	0	0
T320	0	182	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	2921	0	0
T16	843216	131	0	0
T18	0	230	0	0
T79	13829	0	0	0
T106	147083	0	0	0
T131	101717	0	0	0
T220	11859	0	0	0
T226	79624	0	0	0
T229	118548	0	0	0
T230	93221	0	0	0
T231	14079	0	0	0
T243	0	51	0	0
T244	0	76	0	0
T258	104369	0	0	0
T260	0	152	0	0
T312	0	146	0	0
T317	0	74	0	0
T318	0	50	0	0
T319	0	164	0	0
T320	0	188	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	2827	0	0
T16	843216	111	0	0
T18	0	103	0	0
T79	13829	0	0	0
T106	147083	0	0	0
T131	101717	0	0	0
T220	11859	0	0	0
T226	79624	0	0	0
T229	118548	0	0	0
T230	93221	0	0	0
T231	14079	0	0	0
T243	0	84	0	0
T244	0	92	0	0
T258	104369	0	0	0
T260	0	203	0	0
T312	0	135	0	0
T317	0	98	0	0
T318	0	71	0	0
T319	0	164	0	0
T320	0	173	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429060514	2681	0	0
T16	843216	88	0	0
T18	0	171	0	0
T79	13829	0	0	0
T106	147083	0	0	0
T131	101717	0	0	0
T220	11859	0	0	0
T226	79624	0	0	0
T229	118548	0	0	0
T230	93221	0	0	0
T231	14079	0	0	0
T243	0	59	0	0
T244	0	78	0	0
T258	104369	0	0	0
T260	0	206	0	0
T312	0	103	0	0
T317	0	90	0	0
T318	0	50	0	0
T319	0	188	0	0
T320	0	166	0	0