Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.22			95.22

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy	77.78			77.78
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ	80.80			80.80
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty	80.80			80.80
tb.dut.u_otp_ctrl_dai.u_prim_count	80.95			80.95
tb.dut.u_otp_ctrl_scrmbl.u_prim_count	100.00			100.00
tb.dut.u_otp_ctrl_lci.u_prim_count	100.00			100.00
tb.dut.u_otp_ctrl_kdi.u_prim_count_seed	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_count	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_count	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_count	100.00			100.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_count	100.00			100.00

---

Module Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.78			77.78

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.78			77.78

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.36	99.32	100.00		86.36	91.11	100.00	u_otp_ctrl_kdi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.80			80.80

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.80			80.80

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.16	100.00	89.61		100.00	91.18	100.00	u_otp_ctrl_lfsr_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.80			80.80

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.80			80.80

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.16	100.00	89.61		100.00	91.18	100.00	u_otp_ctrl_lfsr_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_dai.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.95			80.95

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.95			80.95

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.38	95.88	95.06		85.96	90.00	100.00	u_otp_ctrl_dai

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	91.67	100.00		100.00	100.00	100.00	u_otp_ctrl_scrmbl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_lci.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00		100.00	100.00	100.00	u_otp_ctrl_lci

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_seed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.36	99.32	100.00		86.36	91.11	100.00	u_otp_ctrl_kdi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.82	97.64	95.24		92.00	96.36	82.86	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.75	95.45	92.86		91.67	90.91	82.86	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.09	98.00	93.75		88.89	95.38	94.44	gen_partitions[7].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.65	98.00	93.75		91.67	95.38	94.44	gen_partitions[8].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	96.00	93.75		91.67	93.85	94.44	gen_partitions[9].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.90	96.91	100.00		95.24	100.00	82.35	gen_partitions[10].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=8,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
80.95	80.95

tb.dut.u_otp_ctrl_dai.u_prim_count

	Total	Covered	Percent
Totals	7	5	71.43
Total Bits	42	34	80.95
Total Bits 0->1	21	17	80.95
Total Bits 1->0	21	17	80.95

Ports	7	5	71.43
Port Bits	42	34	80.95
Port Bits 0->1	21	17	80.95
Port Bits 1->0	21	17	80.95

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_o[7:6]	No	No		No		OUTPUT
cnt_after_commit_o[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[7:6]	No	No		No		OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

*Tests covering at least one bit in the range

---

Toggle Coverage for Module : prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_otp_ctrl_kdi.u_prim_count_seed

SCORE	TOGGLE
77.78	77.78

tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	7	7	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=3,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	22	22	100.00
Total Bits 0->1	11	11	100.00
Total Bits 1->0	11	11	100.00

Ports	7	7	100.00
Port Bits	22	22	100.00
Port Bits 0->1	11	11	100.00
Port Bits 1->0	11	11	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=40,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
80.80	80.80

tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ

SCORE	TOGGLE
80.80	80.80

tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	250	202	80.80
Total Bits 0->1	125	101	80.80
Total Bits 1->0	125	101	80.80

Ports	8	5	62.50
Port Bits	250	202	80.80
Port Bits 0->1	125	101	80.80
Port Bits 1->0	125	101	80.80

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[31:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	INPUT
set_cnt_i[39:32]	No	No		No		INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
step_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[31:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_o[39:32]	No	No		No		OUTPUT
cnt_after_commit_o[31:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[39:32]	No	No		No		OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

*Tests covering at least one bit in the range

---

Toggle Coverage for Module : prim_count ( parameter Width=4,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_count

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_count

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=6,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_otp_ctrl_lci.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	34	34	100.00
Total Bits 0->1	17	17	100.00
Total Bits 1->0	17	17	100.00

Ports	7	7	100.00
Port Bits	34	34	100.00
Port Bits 0->1	17	17	100.00
Port Bits 1->0	17	17	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[5:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[5:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=5,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_otp_ctrl_scrmbl.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	30	30	100.00
Total Bits 0->1	15	15	100.00
Total Bits 1->0	15	15	100.00

Ports	7	7	100.00
Port Bits	30	30	100.00
Port Bits 0->1	15	15	100.00
Port Bits 1->0	15	15	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=1,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	14	14	100.00
Total Bits 0->1	7	7	100.00
Total Bits 1->0	7	7	100.00

Ports	7	7	100.00
Port Bits	14	14	100.00
Port Bits 0->1	7	7	100.00
Port Bits 1->0	7	7	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy

	Total	Covered	Percent
Totals	7	5	71.43
Total Bits	18	14	77.78
Total Bits 0->1	9	7	77.78
Total Bits 1->0	9	7	77.78

Ports	7	5	71.43
Port Bits	18	14	77.78
Port Bits 0->1	9	7	77.78
Port Bits 1->0	9	7	77.78

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
cnt_o[1]	No	No		No		OUTPUT
cnt_after_commit_o[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[1]	No	No		No		OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	250	202	80.80
Total Bits 0->1	125	101	80.80
Total Bits 1->0	125	101	80.80

Ports	8	5	62.50
Port Bits	250	202	80.80
Port Bits 0->1	125	101	80.80
Port Bits 1->0	125	101	80.80

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[31:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	INPUT
set_cnt_i[39:32]	No	No		No		INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
step_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[31:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_o[39:32]	No	No		No		OUTPUT
cnt_after_commit_o[31:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[39:32]	No	No		No		OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	250	202	80.80
Total Bits 0->1	125	101	80.80
Total Bits 1->0	125	101	80.80

Ports	8	5	62.50
Port Bits	250	202	80.80
Port Bits 0->1	125	101	80.80
Port Bits 1->0	125	101	80.80

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T1,T8,T9	Yes	T1,T8,T9	INPUT
set_cnt_i[31:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	INPUT
set_cnt_i[39:32]	No	No		No		INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T1,T8,T9	Yes	T1,T8,T9	INPUT
step_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[31:0]	Yes	Yes	*T1,*T8,*T9	Yes	T1,T8,T9	OUTPUT
cnt_o[39:32]	No	No		No		OUTPUT
cnt_after_commit_o[31:0]	Yes	Yes	*T1,*T8,*T9	Yes	T1,T8,T9	OUTPUT
cnt_after_commit_o[39:32]	No	No		No		OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_prim_count

	Total	Covered	Percent
Totals	7	5	71.43
Total Bits	42	34	80.95
Total Bits 0->1	21	17	80.95
Total Bits 1->0	21	17	80.95

Ports	7	5	71.43
Port Bits	42	34	80.95
Port Bits 0->1	21	17	80.95
Port Bits 1->0	21	17	80.95

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_o[7:6]	No	No		No		OUTPUT
cnt_after_commit_o[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[7:6]	No	No		No		OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	30	30	100.00
Total Bits 0->1	15	15	100.00
Total Bits 1->0	15	15	100.00

Ports	7	7	100.00
Port Bits	30	30	100.00
Port Bits 0->1	15	15	100.00
Port Bits 1->0	15	15	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lci.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	34	34	100.00
Total Bits 0->1	17	17	100.00
Total Bits 1->0	17	17	100.00

Ports	7	7	100.00
Port Bits	34	34	100.00
Port Bits 0->1	17	17	100.00
Port Bits 1->0	17	17	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[5:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[5:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_seed

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	7	7	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	14	14	100.00
Total Bits 0->1	7	7	100.00
Total Bits 1->0	7	7	100.00

Ports	7	7	100.00
Port Bits	14	14	100.00
Port Bits 0->1	7	7	100.00
Port Bits 1->0	7	7	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	22	22	100.00
Total Bits 0->1	11	11	100.00
Total Bits 1->0	11	11	100.00

Ports	7	7	100.00
Port Bits	22	22	100.00
Port Bits 0->1	11	11	100.00
Port Bits 1->0	11	11	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T8,T9	Yes	T1,T8,T9	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT