Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 6852820 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 6469700 1 T1 211 T2 2187 T3 15091



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 8003012 1 T1 714 T2 4318 T3 36568
values[0x0] 2034727 1 T1 107 T2 331 T3 3420
values[0x1] 3284781 1 T1 116 T2 314 T3 3488



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4491582 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 8830938 1 T1 433 T2 2800 T3 22040



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 50527 1 T1 1 T3 168 T4 15
valid_sources[0x01] 52134 1 T1 5 T3 180 T4 10
valid_sources[0x02] 54716 1 T1 6 T3 178 T4 13
valid_sources[0x03] 55450 1 T1 4 T3 169 T4 12
valid_sources[0x04] 47943 1 T1 6 T3 191 T4 13
valid_sources[0x05] 45852 1 T1 7 T3 190 T4 18
valid_sources[0x06] 44913 1 T1 5 T3 148 T4 9
valid_sources[0x07] 46955 1 T1 2 T3 124 T4 10
valid_sources[0x08] 46327 1 T1 3 T3 176 T4 7
valid_sources[0x09] 47103 1 T1 2 T3 121 T4 10
valid_sources[0x0a] 55201 1 T1 6 T3 170 T4 12
valid_sources[0x0b] 51686 1 T1 3 T3 150 T4 6
valid_sources[0x0c] 50949 1 T1 5 T3 164 T4 6
valid_sources[0x0d] 48483 1 T1 4 T3 182 T4 21
valid_sources[0x0e] 44562 1 T1 2 T3 172 T4 19
valid_sources[0x0f] 50300 1 T1 3 T3 187 T4 12
valid_sources[0x10] 54727 1 T1 6 T3 155 T4 16
valid_sources[0x11] 44866 1 T1 1 T3 119 T4 8
valid_sources[0x12] 47387 1 T1 9 T3 144 T4 7
valid_sources[0x13] 49524 1 T1 4 T3 194 T4 14
valid_sources[0x14] 46147 1 T1 3 T3 159 T4 20
valid_sources[0x15] 57188 1 T1 8 T3 146 T4 14
valid_sources[0x16] 49868 1 T1 1 T3 159 T4 8
valid_sources[0x17] 49728 1 T1 7 T3 147 T4 4
valid_sources[0x18] 53783 1 T1 4 T3 190 T4 14
valid_sources[0x19] 46217 1 T1 2 T3 191 T4 12
valid_sources[0x1a] 45018 1 T1 2 T3 145 T4 11
valid_sources[0x1b] 58968 1 T1 1 T3 173 T4 13
valid_sources[0x1c] 49399 1 T1 1 T3 194 T4 7
valid_sources[0x1d] 69454 1 T1 4 T3 192 T4 17
valid_sources[0x1e] 55301 1 T1 5 T3 158 T4 5
valid_sources[0x1f] 55686 1 T1 2 T3 131 T4 13
valid_sources[0x20] 45631 1 T1 3 T3 138 T4 8
valid_sources[0x21] 48085 1 T1 2 T3 160 T4 9
valid_sources[0x22] 54233 1 T1 7 T3 212 T4 12
valid_sources[0x23] 50707 1 T1 6 T3 158 T4 13
valid_sources[0x24] 50062 1 T1 3 T3 141 T4 12
valid_sources[0x25] 52288 1 T1 4 T3 169 T4 7
valid_sources[0x26] 43509 1 T3 159 T4 10 T5 62
valid_sources[0x27] 48563 1 T1 2 T3 182 T4 11
valid_sources[0x28] 48453 1 T1 4 T3 145 T4 8
valid_sources[0x29] 45330 1 T1 3 T3 211 T4 13
valid_sources[0x2a] 46398 1 T1 5 T3 158 T4 10
valid_sources[0x2b] 51057 1 T1 3 T3 138 T4 18
valid_sources[0x2c] 49201 1 T1 5 T3 202 T4 8
valid_sources[0x2d] 45391 1 T1 4 T3 133 T4 11
valid_sources[0x2e] 57620 1 T3 140 T4 8 T5 61
valid_sources[0x2f] 66800 1 T1 4 T3 162 T4 11
valid_sources[0x30] 53927 1 T1 3 T3 137 T4 7
valid_sources[0x31] 44894 1 T1 4 T3 216 T4 14
valid_sources[0x32] 51869 1 T1 1 T3 187 T4 14
valid_sources[0x33] 50942 1 T1 5 T3 134 T4 14
valid_sources[0x34] 44758 1 T1 5 T3 153 T4 8
valid_sources[0x35] 50214 1 T1 4 T3 181 T9 94
valid_sources[0x36] 50484 1 T3 111 T4 13 T5 84
valid_sources[0x37] 56785 1 T1 3 T3 169 T4 13
valid_sources[0x38] 49321 1 T1 1 T3 185 T4 6
valid_sources[0x39] 47038 1 T1 1 T3 146 T4 18
valid_sources[0x3a] 48910 1 T1 4 T3 174 T4 12
valid_sources[0x3b] 50676 1 T1 2 T3 148 T4 11
valid_sources[0x3c] 46407 1 T1 2 T3 175 T4 14
valid_sources[0x3d] 72553 1 T1 6 T3 102 T4 13
valid_sources[0x3e] 53991 1 T1 3 T3 163 T4 14
valid_sources[0x3f] 50061 1 T1 1 T3 165 T4 9
valid_sources[0x40] 52492 1 T1 3 T3 175 T4 6
valid_sources[0x41] 48578 1 T1 5 T3 146 T4 9
valid_sources[0x42] 53543 1 T1 7 T3 212 T4 8
valid_sources[0x43] 61514 1 T1 6 T3 148 T4 9
valid_sources[0x44] 48420 1 T3 165 T4 11 T5 113
valid_sources[0x45] 45259 1 T1 3 T3 168 T4 10
valid_sources[0x46] 58015 1 T1 7 T3 158 T4 23
valid_sources[0x47] 47056 1 T1 6 T3 195 T4 15
valid_sources[0x48] 44800 1 T1 7 T3 173 T4 11
valid_sources[0x49] 46906 1 T1 3 T3 157 T4 13
valid_sources[0x4a] 59572 1 T1 3 T3 141 T4 15
valid_sources[0x4b] 45862 1 T1 5 T3 152 T4 14
valid_sources[0x4c] 45677 1 T1 4 T3 172 T4 6
valid_sources[0x4d] 53588 1 T1 2 T3 207 T4 8
valid_sources[0x4e] 50345 1 T1 2 T3 163 T4 11
valid_sources[0x4f] 62959 1 T1 5 T3 186 T4 14
valid_sources[0x50] 47465 1 T1 1 T3 219 T4 9
valid_sources[0x51] 43356 1 T1 1 T3 190 T4 14
valid_sources[0x52] 58916 1 T1 7 T3 185 T4 9
valid_sources[0x53] 52812 1 T1 2 T3 157 T4 10
valid_sources[0x54] 62722 1 T1 4 T3 180 T4 16
valid_sources[0x55] 44240 1 T1 2 T3 150 T4 6
valid_sources[0x56] 57241 1 T1 6 T3 177 T4 5
valid_sources[0x57] 47626 1 T1 2 T3 148 T4 7
valid_sources[0x58] 44120 1 T1 1 T3 159 T4 12
valid_sources[0x59] 46718 1 T1 5 T3 174 T4 11
valid_sources[0x5a] 53944 1 T1 3 T3 171 T4 10
valid_sources[0x5b] 54247 1 T1 3 T3 132 T4 12
valid_sources[0x5c] 50319 1 T1 5 T3 162 T4 5
valid_sources[0x5d] 57034 1 T1 4 T3 188 T4 8
valid_sources[0x5e] 50379 1 T1 5 T3 165 T4 3
valid_sources[0x5f] 51049 1 T1 4 T3 148 T4 9
valid_sources[0x60] 50935 1 T1 1 T3 190 T4 12
valid_sources[0x61] 55140 1 T1 5 T3 184 T4 16
valid_sources[0x62] 57694 1 T1 4 T3 165 T4 9
valid_sources[0x63] 45659 1 T1 11 T3 193 T4 17
valid_sources[0x64] 49889 1 T1 5 T3 202 T4 14
valid_sources[0x65] 45670 1 T1 3 T3 118 T4 17
valid_sources[0x66] 59889 1 T1 4 T3 135 T4 10
valid_sources[0x67] 50358 1 T1 4 T3 129 T4 15
valid_sources[0x68] 53846 1 T1 3 T3 164 T4 21
valid_sources[0x69] 53199 1 T1 5 T3 195 T4 10
valid_sources[0x6a] 44458 1 T1 2 T3 171 T4 14
valid_sources[0x6b] 53554 1 T1 3 T3 177 T4 7
valid_sources[0x6c] 58161 1 T3 123 T4 15 T5 65
valid_sources[0x6d] 53441 1 T1 2 T3 195 T4 16
valid_sources[0x6e] 48494 1 T1 5 T3 180 T4 9
valid_sources[0x6f] 45592 1 T1 6 T3 216 T9 13
valid_sources[0x70] 44371 1 T1 2 T3 207 T4 13
valid_sources[0x71] 51015 1 T1 2 T2 4963 T3 169
valid_sources[0x72] 53042 1 T1 3 T3 144 T4 8
valid_sources[0x73] 45179 1 T1 4 T3 122 T8 495
valid_sources[0x74] 56142 1 T1 3 T3 182 T4 18
valid_sources[0x75] 79154 1 T1 3 T3 166 T4 9
valid_sources[0x76] 50474 1 T1 4 T3 165 T4 17
valid_sources[0x77] 63593 1 T1 4 T3 219 T4 14
valid_sources[0x78] 44493 1 T1 11 T3 160 T4 11
valid_sources[0x79] 55925 1 T1 4 T3 161 T4 13
valid_sources[0x7a] 53514 1 T1 3 T3 134 T4 11
valid_sources[0x7b] 46834 1 T1 3 T3 129 T4 18
valid_sources[0x7c] 56288 1 T1 7 T3 205 T4 12
valid_sources[0x7d] 51426 1 T1 3 T3 141 T4 13
valid_sources[0x7e] 53678 1 T1 3 T3 151 T4 6
valid_sources[0x7f] 51643 1 T1 1 T3 219 T4 14
valid_sources[0x80] 53275 1 T1 1 T3 204 T4 13



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 3200500 1 T1 108 T2 1899 T3 12621
values[0x0] all_enables biggest_size 1670877 1 T1 62 T2 180 T3 1526
values[0x1] all_enables biggest_size 1598323 1 T1 41 T2 108 T3 944


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 216905 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 7766109 1 T2 120 T3 880 T4 40



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1994174 1 T2 60 T3 440 T4 20
values[0x0] 2907062 1 T2 29 T3 229 T4 12
values[0x1] 3081778 1 T2 31 T3 211 T4 8



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 78719 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 7904295 1 T2 120 T3 880 T4 40



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 30011 1 T38 1 T28 1 T98 1
valid_sources[0x01] 31455 1 T38 1 T28 4 T98 3
valid_sources[0x02] 31596 1 T5 9 T38 3 T16 1
valid_sources[0x03] 32086 1 T2 2 T11 2 T38 2
valid_sources[0x04] 30827 1 T2 2 T11 2 T99 1
valid_sources[0x05] 30320 1 T4 3 T190 1 T99 1
valid_sources[0x06] 29950 1 T97 1 T190 1 T132 2
valid_sources[0x07] 30761 1 T16 1 T98 1 T58 5
valid_sources[0x08] 31289 1 T38 4 T97 1 T132 3
valid_sources[0x09] 30961 1 T99 1 T100 1 T7 179
valid_sources[0x0a] 31585 1 T38 1 T97 1 T16 1
valid_sources[0x0b] 29943 1 T11 3 T97 3 T98 3
valid_sources[0x0c] 32211 1 T38 3 T28 2 T97 2
valid_sources[0x0d] 31584 1 T38 1 T28 3 T97 1
valid_sources[0x0e] 31022 1 T28 2 T98 1 T132 1
valid_sources[0x0f] 31676 1 T11 5 T97 2 T16 1
valid_sources[0x10] 30016 1 T5 4 T38 1 T132 1
valid_sources[0x11] 31687 1 T2 1 T38 1 T28 1
valid_sources[0x12] 29849 1 T38 1 T98 1 T99 1
valid_sources[0x13] 33150 1 T38 3 T16 1 T98 3
valid_sources[0x14] 31748 1 T11 5 T38 2 T28 3
valid_sources[0x15] 30205 1 T2 1 T38 1 T16 2
valid_sources[0x16] 33144 1 T2 5 T38 1 T91 3
valid_sources[0x17] 31126 1 T38 1 T91 2 T96 2
valid_sources[0x18] 31422 1 T28 1 T97 1 T189 1
valid_sources[0x19] 29302 1 T4 1 T98 2 T189 3
valid_sources[0x1a] 31170 1 T97 1 T189 2 T99 1
valid_sources[0x1b] 32500 1 T2 2 T28 1 T189 2
valid_sources[0x1c] 34542 1 T11 1 T38 2 T16 2
valid_sources[0x1d] 30700 1 T38 1 T28 1 T16 1
valid_sources[0x1e] 29562 1 T38 1 T16 1 T98 1
valid_sources[0x1f] 32359 1 T2 1 T38 2 T28 1
valid_sources[0x20] 31250 1 T38 1 T28 3 T16 1
valid_sources[0x21] 29905 1 T2 1 T28 2 T98 1
valid_sources[0x22] 29447 1 T11 3 T38 2 T190 4
valid_sources[0x23] 30924 1 T11 3 T38 1 T28 3
valid_sources[0x24] 31152 1 T5 5 T11 4 T96 1
valid_sources[0x25] 31067 1 T2 1 T38 1 T28 1
valid_sources[0x26] 32455 1 T38 1 T16 1 T98 2
valid_sources[0x27] 31440 1 T2 1 T16 1 T132 2
valid_sources[0x28] 31377 1 T11 1 T28 1 T16 1
valid_sources[0x29] 31202 1 T4 1 T190 1 T98 1
valid_sources[0x2a] 30533 1 T28 4 T16 2 T189 1
valid_sources[0x2b] 29837 1 T38 1 T28 1 T95 1
valid_sources[0x2c] 31445 1 T4 2 T28 4 T243 2
valid_sources[0x2d] 32049 1 T2 2 T28 3 T16 1
valid_sources[0x2e] 31168 1 T2 1 T98 2 T96 1
valid_sources[0x2f] 30700 1 T132 1 T96 1 T99 2
valid_sources[0x30] 32272 1 T2 1 T38 2 T98 3
valid_sources[0x31] 30809 1 T2 1 T28 1 T29 1
valid_sources[0x32] 31194 1 T98 1 T132 1 T96 2
valid_sources[0x33] 30506 1 T11 2 T96 1 T100 2
valid_sources[0x34] 32190 1 T28 2 T29 1 T216 2
valid_sources[0x35] 30620 1 T38 1 T189 1 T99 1
valid_sources[0x36] 32846 1 T249 120 T29 2 T7 153
valid_sources[0x37] 31181 1 T38 1 T97 3 T16 1
valid_sources[0x38] 30505 1 T38 2 T58 5 T95 1
valid_sources[0x39] 30742 1 T2 3 T38 1 T16 2
valid_sources[0x3a] 31238 1 T38 2 T16 1 T98 3
valid_sources[0x3b] 31179 1 T4 3 T38 2 T28 1
valid_sources[0x3c] 30245 1 T2 1 T38 1 T28 2
valid_sources[0x3d] 30907 1 T2 4 T16 1 T189 1
valid_sources[0x3e] 30091 1 T38 1 T98 1 T189 1
valid_sources[0x3f] 30576 1 T38 3 T98 1 T96 1
valid_sources[0x40] 31497 1 T4 4 T190 7 T16 3
valid_sources[0x41] 30366 1 T4 2 T98 1 T189 1
valid_sources[0x42] 32811 1 T11 3 T38 1 T28 3
valid_sources[0x43] 31597 1 T38 2 T98 2 T204 2
valid_sources[0x44] 30702 1 T28 1 T97 2 T98 2
valid_sources[0x45] 29932 1 T4 1 T38 4 T28 4
valid_sources[0x46] 30401 1 T28 4 T190 1 T16 1
valid_sources[0x47] 29817 1 T5 15 T28 1 T98 1
valid_sources[0x48] 29799 1 T38 1 T28 1 T204 2
valid_sources[0x49] 30592 1 T2 3 T28 1 T243 1
valid_sources[0x4a] 30652 1 T38 1 T97 2 T190 1
valid_sources[0x4b] 31185 1 T2 1 T5 11 T11 12
valid_sources[0x4c] 30497 1 T99 1 T7 213 T13 133
valid_sources[0x4d] 31142 1 T5 2 T38 1 T16 1
valid_sources[0x4e] 30556 1 T11 2 T96 1 T398 1
valid_sources[0x4f] 30070 1 T38 1 T243 1 T99 2
valid_sources[0x50] 30469 1 T38 1 T28 1 T98 2
valid_sources[0x51] 32380 1 T11 7 T38 1 T28 1
valid_sources[0x52] 29573 1 T11 2 T38 1 T28 2
valid_sources[0x53] 33093 1 T2 1 T38 1 T28 1
valid_sources[0x54] 31309 1 T38 1 T97 1 T132 3
valid_sources[0x55] 32061 1 T28 1 T96 1 T99 1
valid_sources[0x56] 30522 1 T126 1 T96 1 T99 3
valid_sources[0x57] 32994 1 T189 1 T126 2 T29 5
valid_sources[0x58] 30147 1 T126 1 T132 2 T58 2
valid_sources[0x59] 31904 1 T190 3 T98 2 T132 2
valid_sources[0x5a] 31233 1 T5 18 T189 1 T91 4
valid_sources[0x5b] 30745 1 T16 1 T91 3 T96 1
valid_sources[0x5c] 30680 1 T2 1 T189 1 T96 3
valid_sources[0x5d] 32841 1 T2 2 T38 1 T96 1
valid_sources[0x5e] 31514 1 T97 2 T132 2 T99 3
valid_sources[0x5f] 31494 1 T11 3 T97 1 T190 5
valid_sources[0x60] 30015 1 T3 880 T11 1 T28 1
valid_sources[0x61] 31734 1 T29 2 T6 2 T7 150
valid_sources[0x62] 33193 1 T28 4 T16 1 T132 3
valid_sources[0x63] 30500 1 T38 1 T91 2 T100 2
valid_sources[0x64] 30620 1 T11 3 T132 1 T96 1
valid_sources[0x65] 30668 1 T5 3 T28 1 T16 2
valid_sources[0x66] 29879 1 T28 2 T189 1 T58 2
valid_sources[0x67] 32095 1 T97 1 T16 1 T98 1
valid_sources[0x68] 31651 1 T38 1 T16 1 T126 1
valid_sources[0x69] 31260 1 T11 1 T38 1 T189 1
valid_sources[0x6a] 31655 1 T28 3 T98 2 T189 1
valid_sources[0x6b] 31310 1 T2 1 T38 1 T97 4
valid_sources[0x6c] 30911 1 T97 2 T16 1 T99 1
valid_sources[0x6d] 33479 1 T2 2 T28 2 T97 1
valid_sources[0x6e] 31045 1 T2 1 T28 3 T29 3
valid_sources[0x6f] 30673 1 T28 2 T97 4 T190 2
valid_sources[0x70] 30874 1 T2 3 T28 2 T97 2
valid_sources[0x71] 30489 1 T38 1 T28 1 T98 1
valid_sources[0x72] 30750 1 T28 1 T190 2 T189 1
valid_sources[0x73] 29941 1 T2 1 T38 1 T243 1
valid_sources[0x74] 31193 1 T28 1 T16 1 T98 4
valid_sources[0x75] 31555 1 T2 1 T28 5 T97 1
valid_sources[0x76] 30726 1 T2 2 T16 1 T98 1
valid_sources[0x77] 32485 1 T5 1 T98 1 T126 1
valid_sources[0x78] 30554 1 T132 1 T96 1 T7 150
valid_sources[0x79] 31858 1 T28 2 T190 1 T99 1
valid_sources[0x7a] 32097 1 T38 1 T28 1 T16 4
valid_sources[0x7b] 32268 1 T11 4 T189 1 T96 2
valid_sources[0x7c] 31566 1 T11 1 T38 2 T91 2
valid_sources[0x7d] 29996 1 T38 2 T97 1 T132 3
valid_sources[0x7e] 31373 1 T2 5 T11 1 T38 1
valid_sources[0x7f] 32739 1 T38 1 T190 1 T16 1
valid_sources[0x80] 31546 1 T2 1 T38 1 T28 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 1980598 1 T2 60 T3 440 T4 20
values[0x0] all_enables biggest_size 2892259 1 T2 29 T3 229 T4 12
values[0x1] all_enables biggest_size 2893252 1 T2 31 T3 211 T4 8

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