Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

22409485

1

T1

726

T2

2776

T3

28385

full_word

7409958

1

T1

211

T2

2187

T3

15091

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29819143	1			T1	937		T2	4963		T3	43476
auto[TlIntgErrCmd]	103	1			T250	2		T251	4		T252	3
auto[TlIntgErrData]	94	1			T250	4		T251	1		T252	7
auto[TlIntgErrBoth]	103	1			T250	4		T251	5		T252	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9140881

1

T1

714

T2

4318

T3

36568

auto[1]

20678562

1

T1

223

T2

645

T3

6908

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5825098	1			T1	606		T2	2419		T3	23947
auto[TlIntgErrNone]	partial	auto[1]	16584114	1			T1	120		T2	357		T3	4438
auto[TlIntgErrNone]	full_word	auto[0]	3315643	1			T1	108		T2	1899		T3	12621
auto[TlIntgErrNone]	full_word	auto[1]	4094288	1			T1	103		T2	288		T3	2470
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T251	2		T252	1		T356	4
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T250	1		T251	2		T252	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T357	1		T362	1		T363	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T250	1		T361	1		T364	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T250	3		T251	1		T252	1
auto[TlIntgErrData]	partial	auto[1]	36	1			T250	1		T252	6		T356	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T356	1		T357	1		T361	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T362	1		T363	1		T361	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T250	2		T251	3		T252	6
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T250	2		T251	2		T252	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T252	1		T360	1		T365	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T358	1		T366	1		T367	1