Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.35	94.81	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	416260694	6976735	0	0
check_regwen_rd_A	416260694	3417	0	0
check_timeout_rd_A	416260694	2252	0	0
check_trigger_regwen_rd_A	416260694	3256	0	0
consistency_check_period_rd_A	416260694	3573	0	0
creator_sw_cfg_read_lock_rd_A	416260694	2087	0	0
direct_access_address_rd_A	416260694	1965	0	0
direct_access_wdata_0_rd_A	416260694	1209	0	0
direct_access_wdata_1_rd_A	416260694	1433	0	0
integrity_check_period_rd_A	416260694	3474	0	0
intr_enable_rd_A	416260694	4302	0	0
owner_sw_cfg_read_lock_rd_A	416260694	2097	0	0
rot_creator_auth_codesign_read_lock_rd_A	416260694	2139	0	0
rot_creator_auth_state_read_lock_rd_A	416260694	2070	0	0
vendor_test_read_lock_rd_A	416260694	2027	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	6976735	0	0
T7	265037	38086	0	0
T13	156410	31767	0	0
T14	0	11824	0	0
T15	49635	0	0	0
T17	0	133986	0	0
T27	0	146821	0	0
T33	17835	0	0	0
T102	124698	0	0	0
T128	0	183570	0	0
T160	12201	0	0	0
T213	4881	0	0	0
T214	0	169805	0	0
T215	0	67094	0	0
T234	0	28652	0	0
T240	0	82353	0	0
T242	15236	0	0	0
T259	16992	0	0	0
T260	23086	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	3417	0	0
T18	0	125	0	0
T19	0	37	0	0
T49	15203	0	0	0
T74	0	102	0	0
T80	26661	0	0	0
T108	12003	0	0	0
T115	0	53	0	0
T166	218092	78	0	0
T167	10165	0	0	0
T244	24250	0	0	0
T319	0	100	0	0
T320	0	70	0	0
T321	0	64	0	0
T322	0	116	0	0
T323	0	53	0	0
T324	400614	0	0	0
T325	72099	0	0	0
T326	51025	0	0	0
T327	58637	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	2252	0	0
T18	0	129	0	0
T19	0	69	0	0
T49	15203	0	0	0
T74	0	97	0	0
T80	26661	0	0	0
T108	12003	0	0	0
T115	0	104	0	0
T166	218092	88	0	0
T167	10165	0	0	0
T244	24250	0	0	0
T319	0	122	0	0
T320	0	95	0	0
T321	0	55	0	0
T322	0	144	0	0
T323	0	74	0	0
T324	400614	0	0	0
T325	72099	0	0	0
T326	51025	0	0	0
T327	58637	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	3256	0	0
T18	0	96	0	0
T19	0	33	0	0
T49	15203	0	0	0
T74	0	81	0	0
T80	26661	0	0	0
T108	12003	0	0	0
T115	0	81	0	0
T166	218092	63	0	0
T167	10165	0	0	0
T244	24250	0	0	0
T319	0	69	0	0
T320	0	42	0	0
T321	0	64	0	0
T322	0	108	0	0
T323	0	42	0	0
T324	400614	0	0	0
T325	72099	0	0	0
T326	51025	0	0	0
T327	58637	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	3573	0	0
T18	0	130	0	0
T19	0	23	0	0
T49	15203	0	0	0
T74	0	70	0	0
T80	26661	0	0	0
T108	12003	0	0	0
T115	0	98	0	0
T166	218092	62	0	0
T167	10165	0	0	0
T244	24250	0	0	0
T319	0	130	0	0
T320	0	82	0	0
T321	0	67	0	0
T322	0	116	0	0
T323	0	76	0	0
T324	400614	0	0	0
T325	72099	0	0	0
T326	51025	0	0	0
T327	58637	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	2087	0	0
T18	0	109	0	0
T19	0	76	0	0
T49	15203	0	0	0
T74	0	80	0	0
T80	26661	0	0	0
T108	12003	0	0	0
T115	0	54	0	0
T166	218092	78	0	0
T167	10165	0	0	0
T244	24250	0	0	0
T319	0	120	0	0
T320	0	61	0	0
T321	0	69	0	0
T322	0	142	0	0
T323	0	32	0	0
T324	400614	0	0	0
T325	72099	0	0	0
T326	51025	0	0	0
T327	58637	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	1965	0	0
T18	0	125	0	0
T19	0	81	0	0
T49	15203	0	0	0
T74	0	94	0	0
T80	26661	0	0	0
T108	12003	0	0	0
T115	0	84	0	0
T166	218092	114	0	0
T167	10165	0	0	0
T244	24250	0	0	0
T319	0	149	0	0
T320	0	42	0	0
T321	0	86	0	0
T322	0	121	0	0
T323	0	37	0	0
T324	400614	0	0	0
T325	72099	0	0	0
T326	51025	0	0	0
T327	58637	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	1209	0	0
T18	0	58	0	0
T19	0	16	0	0
T49	15203	0	0	0
T74	0	49	0	0
T80	26661	0	0	0
T108	12003	0	0	0
T115	0	67	0	0
T166	218092	11	0	0
T167	10165	0	0	0
T244	24250	0	0	0
T319	0	115	0	0
T320	0	34	0	0
T321	0	32	0	0
T322	0	125	0	0
T323	0	24	0	0
T324	400614	0	0	0
T325	72099	0	0	0
T326	51025	0	0	0
T327	58637	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	1433	0	0
T18	0	51	0	0
T19	0	57	0	0
T49	15203	0	0	0
T74	0	57	0	0
T80	26661	0	0	0
T108	12003	0	0	0
T115	0	62	0	0
T166	218092	26	0	0
T167	10165	0	0	0
T244	24250	0	0	0
T319	0	107	0	0
T320	0	65	0	0
T321	0	49	0	0
T322	0	131	0	0
T323	0	46	0	0
T324	400614	0	0	0
T325	72099	0	0	0
T326	51025	0	0	0
T327	58637	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	3474	0	0
T18	0	125	0	0
T19	0	84	0	0
T49	15203	0	0	0
T74	0	80	0	0
T80	26661	0	0	0
T108	12003	0	0	0
T115	0	57	0	0
T166	218092	74	0	0
T167	10165	0	0	0
T244	24250	0	0	0
T319	0	103	0	0
T320	0	62	0	0
T321	0	63	0	0
T322	0	116	0	0
T323	0	46	0	0
T324	400614	0	0	0
T325	72099	0	0	0
T326	51025	0	0	0
T327	58637	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	4302	0	0
T18	0	106	0	0
T19	0	92	0	0
T116	143567	41	0	0
T117	531060	5	0	0
T166	0	91	0	0
T181	14340	0	0	0
T319	0	106	0	0
T320	0	93	0	0
T321	0	81	0	0
T328	0	10	0	0
T329	0	34	0	0
T330	10959	0	0	0
T331	68917	0	0	0
T332	14999	0	0	0
T333	19245	0	0	0
T334	65107	0	0	0
T335	105288	0	0	0
T336	10795	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	2097	0	0
T18	0	123	0	0
T19	0	52	0	0
T49	15203	0	0	0
T74	0	86	0	0
T80	26661	0	0	0
T108	12003	0	0	0
T115	0	45	0	0
T166	218092	67	0	0
T167	10165	0	0	0
T244	24250	0	0	0
T319	0	119	0	0
T320	0	73	0	0
T321	0	90	0	0
T322	0	131	0	0
T323	0	36	0	0
T324	400614	0	0	0
T325	72099	0	0	0
T326	51025	0	0	0
T327	58637	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	2139	0	0
T18	0	121	0	0
T19	0	42	0	0
T49	15203	0	0	0
T74	0	71	0	0
T80	26661	0	0	0
T108	12003	0	0	0
T115	0	63	0	0
T166	218092	69	0	0
T167	10165	0	0	0
T244	24250	0	0	0
T319	0	140	0	0
T320	0	69	0	0
T321	0	52	0	0
T322	0	118	0	0
T323	0	90	0	0
T324	400614	0	0	0
T325	72099	0	0	0
T326	51025	0	0	0
T327	58637	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	2070	0	0
T18	0	130	0	0
T19	0	39	0	0
T49	15203	0	0	0
T74	0	96	0	0
T80	26661	0	0	0
T108	12003	0	0	0
T115	0	101	0	0
T166	218092	88	0	0
T167	10165	0	0	0
T244	24250	0	0	0
T319	0	90	0	0
T320	0	82	0	0
T321	0	42	0	0
T322	0	137	0	0
T323	0	39	0	0
T324	400614	0	0	0
T325	72099	0	0	0
T326	51025	0	0	0
T327	58637	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416260694	2027	0	0
T18	0	90	0	0
T19	0	68	0	0
T49	15203	0	0	0
T74	0	123	0	0
T80	26661	0	0	0
T108	12003	0	0	0
T115	0	70	0	0
T166	218092	111	0	0
T167	10165	0	0	0
T244	24250	0	0	0
T319	0	159	0	0
T320	0	56	0	0
T321	0	45	0	0
T322	0	110	0	0
T323	0	39	0	0
T324	400614	0	0	0
T325	72099	0	0	0
T326	51025	0	0	0
T327	58637	0	0	0