Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	100.00	100.00		85.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.73	100.00	100.00	100.00	85.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.35	94.81	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.35	94.81	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.35	94.81	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T3,T8
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T157
1	Covered	T157

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T5

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T8
ReadWaitSt	252	Covered	T1,T3,T8
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T3,T8
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T117,T193,T194
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T10,T5
ReadSt->ReadWaitSt	252	Covered	T1,T3,T8
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T3,T8
ResetSt->ErrorSt	315	Covered	T79,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T3,T10,T5
CheckFailError	317	Covered	T157
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T153,T189,T6
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T3,T10,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T157
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T3,T10,T5
NoError->CheckFailError	317	Covered	T157
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T8
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T8
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T96,T111
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T10,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T157
1	0	Covered	T157
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	413327737	412465814	0	0
DigestKnown_A	413327737	412465814	0	0
DigestOffsetMustBeRepresentable_A	1143	1143	0	0
EccErrorState_A	413327737	2797	0	0
ErrorKnown_A	413327737	412465814	0	0
FsmStateKnown_A	413327737	412465814	0	0
InitDoneKnown_A	413327737	412465814	0	0
InitReadLocksPartition_A	413327737	87098074	0	0
InitWriteLocksPartition_A	413327737	87098074	0	0
OffsetMustBeBlockAligned_A	1143	1143	0	0
OtpAddrKnown_A	413327737	412465814	0	0
OtpCmdKnown_A	413327737	412465814	0	0
OtpErrorState_A	413327737	0	0	0
OtpReqKnown_A	413327737	412465814	0	0
OtpSizeKnown_A	413327737	412465814	0	0
OtpWdataKnown_A	413327737	412465814	0	0
ReadLockPropagation_A	413327737	177832037	0	0
SizeMustBeBlockAligned_A	1143	1143	0	0
TlulGntKnown_A	413327737	412465814	0	0
TlulRdataKnown_A	413327737	412465814	0	0
TlulReadOnReadLock_A	413327737	7632	0	0
TlulRerrorKnown_A	413327737	412465814	0	0
TlulRvalidKnown_A	413327737	412465814	0	0
WriteLockPropagation_A	413327737	2737264	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	413327737	30883766	0	0
u_state_regs_A	413327737	412465814	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	2797	0	0
T72	9423	0	0	0
T157	9636	2797	0	0
T168	24261	0	0	0
T169	8140	0	0	0
T170	63477	0	0	0
T171	8942	0	0	0
T172	186491	0	0	0
T173	9781	0	0	0
T174	13723	0	0	0
T175	12600	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	87098074	0	0
T1	10220	5086	0	0
T2	55365	9521	0	0
T3	810642	123489	0	0
T4	24914	381	0	0
T5	670883	88494	0	0
T8	15226	6826	0	0
T9	14820	3284	0	0
T10	77406	2200	0	0
T11	163838	15598	0	0
T12	10063	3884	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	87098074	0	0
T1	10220	5086	0	0
T2	55365	9521	0	0
T3	810642	123489	0	0
T4	24914	381	0	0
T5	670883	88494	0	0
T8	15226	6826	0	0
T9	14820	3284	0	0
T10	77406	2200	0	0
T11	163838	15598	0	0
T12	10063	3884	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	177832037	0	0
T3	810642	164961	0	0
T4	24914	0	0	0
T5	670883	94290	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	10718	0	0
T11	163838	2717	0	0
T12	10063	0	0	0
T16	0	3440	0	0
T28	0	4281	0	0
T38	0	32349	0	0
T76	0	33638	0	0
T97	0	8687	0	0
T103	14453	0	0	0
T104	122681	0	0	0
T153	0	3189	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	7632	0	0
T2	55365	7	0	0
T3	810642	38	0	0
T4	24914	0	0	0
T5	670883	17	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	3	0	0
T11	163838	4	0	0
T12	10063	0	0	0
T28	0	1	0	0
T38	0	10	0	0
T97	0	1	0	0
T103	14453	0	0	0
T104	0	3	0	0
T153	0	26	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	2737264	0	0
T3	810642	22955	0	0
T4	24914	0	0	0
T5	670883	0	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	10039	0	0
T11	163838	0	0	0
T12	10063	0	0	0
T28	0	13596	0	0
T29	0	5127	0	0
T76	0	10120	0	0
T96	0	944	0	0
T99	0	2192	0	0
T100	0	8622	0	0
T101	0	4857	0	0
T102	0	8478	0	0
T103	14453	0	0	0
T104	122681	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	30883766	0	0
T3	810642	440861	0	0
T4	24914	0	0	0
T5	670883	92465	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	60277	0	0
T11	163838	0	0	0
T12	10063	3036	0	0
T16	0	35868	0	0
T28	0	75501	0	0
T38	0	204994	0	0
T97	0	28950	0	0
T103	14453	0	0	0
T104	122681	0	0	0
T176	0	2291	0	0
T177	0	3621	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T158,T86,T159

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T2,T11,T29

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T79,T143
1	Covered	T79,T143

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T5

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T117,T193,T194
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T12,T103,T107
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T5,T38
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T104,T149,T182
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T79,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T5,T38
CheckFailError	317	Covered	T79,T143
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T2,T11,T158
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T3,T5,T153
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T5,T38
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T79,T143
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T2,T158,T86
MacroEccCorrError->NoError	235	Covered	T11,T29,T112
NoError->AccessError	256	Covered	T3,T5,T38
NoError->CheckFailError	317	Covered	T79,T143
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T2,T11,T158

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T158,T86,T159
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T12,T103,T107
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T96,T111
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T38
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T2,T11,T29
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T104,T149,T182
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T79,T143
1	0	Covered	T79,T143
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	413327737	412465814	0	0
DigestKnown_A	413327737	412465814	0	0
DigestOffsetMustBeRepresentable_A	1143	1143	0	0
EccErrorState_A	413327737	7115	0	0
ErrorKnown_A	413327737	412465814	0	0
FsmStateKnown_A	413327737	412465814	0	0
InitDoneKnown_A	413327737	412465814	0	0
InitReadLocksPartition_A	413327737	87278378	0	0
InitWriteLocksPartition_A	413327737	87278378	0	0
OffsetMustBeBlockAligned_A	1143	1143	0	0
OtpAddrKnown_A	413327737	412465814	0	0
OtpCmdKnown_A	413327737	412465814	0	0
OtpErrorState_A	413327737	83	0	0
OtpReqKnown_A	413327737	412465814	0	0
OtpSizeKnown_A	413327737	412465814	0	0
OtpWdataKnown_A	413327737	412465814	0	0
ReadLockPropagation_A	413327737	174560363	0	0
SizeMustBeBlockAligned_A	1143	1143	0	0
TlulGntKnown_A	413327737	412465814	0	0
TlulRdataKnown_A	413327737	412465814	0	0
TlulReadOnReadLock_A	413327737	7868	0	0
TlulRerrorKnown_A	413327737	412465814	0	0
TlulRvalidKnown_A	413327737	412465814	0	0
WriteLockPropagation_A	413327737	2459088	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	413327737	31051538	0	0
u_state_regs_A	413327737	412465814	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	7115	0	0
T49	15203	0	0	0
T79	10661	3836	0	0
T108	12003	0	0	0
T143	0	3279	0	0
T161	15806	0	0	0
T162	17244	0	0	0
T163	52732	0	0	0
T164	23527	0	0	0
T165	13311	0	0	0
T166	218092	0	0	0
T167	10165	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	87278378	0	0
T1	10220	5120	0	0
T2	55365	9793	0	0
T3	810642	125019	0	0
T4	24914	483	0	0
T5	670883	88868	0	0
T8	15226	6860	0	0
T9	14820	3335	0	0
T10	77406	2319	0	0
T11	163838	15870	0	0
T12	10063	3908	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	87278378	0	0
T1	10220	5120	0	0
T2	55365	9793	0	0
T3	810642	125019	0	0
T4	24914	483	0	0
T5	670883	88868	0	0
T8	15226	6860	0	0
T9	14820	3335	0	0
T10	77406	2319	0	0
T11	163838	15870	0	0
T12	10063	3908	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	83	0	0
T12	10063	1	0	0
T28	88604	0	0	0
T38	226405	0	0	0
T70	14796	0	0	0
T92	0	1	0	0
T94	0	1	0	0
T103	14453	1	0	0
T104	122681	1	0	0
T107	14418	1	0	0
T149	0	1	0	0
T153	123468	0	0	0
T155	10347	0	0	0
T176	13811	1	0	0
T177	0	1	0	0
T178	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	174560363	0	0
T3	810642	116371	0	0
T4	24914	0	0	0
T5	670883	112248	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	8462	0	0
T11	163838	1595	0	0
T12	10063	0	0	0
T16	0	3293	0	0
T28	0	16707	0	0
T38	0	49816	0	0
T76	0	16932	0	0
T97	0	2331	0	0
T103	14453	0	0	0
T104	122681	0	0	0
T153	0	3187	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	7868	0	0
T2	55365	9	0	0
T3	810642	34	0	0
T4	24914	0	0	0
T5	670883	25	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	0	0	0
T11	163838	2	0	0
T12	10063	0	0	0
T28	0	1	0	0
T38	0	13	0	0
T76	0	15	0	0
T103	14453	0	0	0
T104	0	8	0	0
T153	0	21	0	0
T190	0	7	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	2459088	0	0
T3	810642	37385	0	0
T4	24914	0	0	0
T5	670883	0	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	17679	0	0
T11	163838	0	0	0
T12	10063	0	0	0
T16	0	3026	0	0
T28	0	19285	0	0
T29	0	8527	0	0
T38	0	37733	0	0
T76	0	9569	0	0
T96	0	4739	0	0
T97	0	4053	0	0
T100	0	4134	0	0
T103	14453	0	0	0
T104	122681	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	31051538	0	0
T3	810642	331544	0	0
T4	24914	0	0	0
T5	670883	92414	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	60192	0	0
T11	163838	152488	0	0
T12	10063	3031	0	0
T28	0	75246	0	0
T38	0	204773	0	0
T103	14453	2620	0	0
T104	122681	0	0	0
T107	0	3573	0	0
T153	0	2471	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T70,T160,T156

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T2,T11,T153

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T79,T143,T157
1	Covered	T79,T143,T157

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T117,T193,T194
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T12,T103,T107
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T10,T5
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T182,T184,T195
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T79,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T10,T5
CheckFailError	317	Covered	T79,T143,T157
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T2,T11,T153
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T153,T189,T6
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T10,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T79,T143,T157
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T2,T153,T70
MacroEccCorrError->NoError	235	Covered	T11,T76,T29
NoError->AccessError	256	Covered	T3,T10,T5
NoError->CheckFailError	317	Covered	T79,T143,T157
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T2,T11,T153

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T70,T160,T156
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T158,T179,T180
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T96,T111
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T10,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T2,T11,T153
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T182,T184,T195
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T79,T143,T157
1	0	Covered	T79,T143,T157
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	413327737	412465814	0	0
DigestKnown_A	413327737	412465814	0	0
DigestOffsetMustBeRepresentable_A	1143	1143	0	0
EccErrorState_A	413327737	9912	0	0
ErrorKnown_A	413327737	412465814	0	0
FsmStateKnown_A	413327737	412465814	0	0
InitDoneKnown_A	413327737	412465814	0	0
InitReadLocksPartition_A	413327737	87457489	0	0
InitWriteLocksPartition_A	413327737	87457489	0	0
OffsetMustBeBlockAligned_A	1143	1143	0	0
OtpAddrKnown_A	413327737	412465814	0	0
OtpCmdKnown_A	413327737	412465814	0	0
OtpErrorState_A	413327737	56	0	0
OtpReqKnown_A	413327737	412465814	0	0
OtpSizeKnown_A	413327737	412465814	0	0
OtpWdataKnown_A	413327737	412465814	0	0
ReadLockPropagation_A	413327737	172878416	0	0
SizeMustBeBlockAligned_A	1143	1143	0	0
TlulGntKnown_A	413327737	412465814	0	0
TlulRdataKnown_A	413327737	412465814	0	0
TlulReadOnReadLock_A	413327737	8092	0	0
TlulRerrorKnown_A	413327737	412465814	0	0
TlulRvalidKnown_A	413327737	412465814	0	0
WriteLockPropagation_A	413327737	1458537	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	413327737	19222771	0	0
u_state_regs_A	413327737	412465814	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	9912	0	0
T49	15203	0	0	0
T79	10661	3836	0	0
T108	12003	0	0	0
T143	0	3279	0	0
T157	0	2797	0	0
T161	15806	0	0	0
T162	17244	0	0	0
T163	52732	0	0	0
T164	23527	0	0	0
T165	13311	0	0	0
T166	218092	0	0	0
T167	10165	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	87457489	0	0
T1	10220	5154	0	0
T2	55365	10065	0	0
T3	810642	126549	0	0
T4	24914	585	0	0
T5	670883	89242	0	0
T8	15226	6894	0	0
T9	14820	3386	0	0
T10	77406	2438	0	0
T11	163838	16142	0	0
T12	10063	3925	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	87457489	0	0
T1	10220	5154	0	0
T2	55365	10065	0	0
T3	810642	126549	0	0
T4	24914	585	0	0
T5	670883	89242	0	0
T8	15226	6894	0	0
T9	14820	3386	0	0
T10	77406	2438	0	0
T11	163838	16142	0	0
T12	10063	3925	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	56	0	0
T16	41682	0	0	0
T66	14042	0	0	0
T76	149117	0	0	0
T84	15900	0	0	0
T98	109382	0	0	0
T126	34842	0	0	0
T132	17053	0	0	0
T158	8797	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	2	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	6317	0	0	0
T189	24671	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	172878416	0	0
T3	810642	125573	0	0
T4	24914	0	0	0
T5	670883	95851	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	14283	0	0
T11	163838	2699	0	0
T12	10063	0	0	0
T16	0	3687	0	0
T28	0	13084	0	0
T38	0	49391	0	0
T76	0	31328	0	0
T97	0	9567	0	0
T103	14453	0	0	0
T104	122681	0	0	0
T153	0	3185	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	8092	0	0
T2	55365	9	0	0
T3	810642	30	0	0
T4	24914	0	0	0
T5	670883	24	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	2	0	0
T11	163838	0	0	0
T12	10063	0	0	0
T28	0	1	0	0
T38	0	14	0	0
T97	0	1	0	0
T103	14453	0	0	0
T104	0	3	0	0
T153	0	25	0	0
T190	0	7	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	1458537	0	0
T3	810642	45091	0	0
T4	24914	0	0	0
T5	670883	0	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	0	0	0
T11	163838	3385	0	0
T12	10063	0	0	0
T76	0	13041	0	0
T97	0	3284	0	0
T98	0	8231	0	0
T103	14453	0	0	0
T104	122681	0	0	0
T105	0	7066	0	0
T111	0	12184	0	0
T112	0	5032	0	0
T191	0	9462	0	0
T192	0	4287	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	19222771	0	0
T2	55365	5224	0	0
T3	810642	438821	0	0
T4	24914	0	0	0
T5	670883	0	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	60107	0	0
T11	163838	152250	0	0
T12	10063	0	0	0
T76	0	130806	0	0
T97	0	36077	0	0
T98	0	90561	0	0
T103	14453	0	0	0
T153	0	2454	0	0
T158	0	3354	0	0
T189	0	2450	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0