Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.35	94.81	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.35	94.81	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T70,T155,T156

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T2,T11,T153

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T79
1	Covered	T79

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T5

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T12,T103,T107
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T158,T93,T159
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T10,T5
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T153,T150,T196
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T79,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T10,T5
CheckFailError	317	Covered	T79
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T2,T11,T153
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T153,T189
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T10,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T79
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T2,T153,T70
MacroEccCorrError->NoError	235	Covered	T11,T29,T77
NoError->AccessError	256	Covered	T3,T10,T5
NoError->CheckFailError	317	Covered	T79
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T2,T11,T153

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T70,T155,T156
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T93,T159,T160
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T96,T111
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T10,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T2,T11,T153
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T153,T150,T196
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T79
1	0	Covered	T79
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	413327737	412465814	0	0
DigestKnown_A	413327737	412465814	0	0
DigestOffsetMustBeRepresentable_A	1143	1143	0	0
EccErrorState_A	413327737	3836	0	0
ErrorKnown_A	413327737	412465814	0	0
FsmStateKnown_A	413327737	412465814	0	0
InitDoneKnown_A	413327737	412465814	0	0
InitReadLocksPartition_A	413327737	87635636	0	0
InitWriteLocksPartition_A	413327737	87635636	0	0
OffsetMustBeBlockAligned_A	1143	1143	0	0
OtpAddrKnown_A	413327737	412465814	0	0
OtpCmdKnown_A	413327737	412465814	0	0
OtpErrorState_A	413327737	46	0	0
OtpReqKnown_A	413327737	412465814	0	0
OtpSizeKnown_A	413327737	412465814	0	0
OtpWdataKnown_A	413327737	412465814	0	0
ReadLockPropagation_A	413327737	178434735	0	0
SizeMustBeBlockAligned_A	1143	1143	0	0
TlulGntKnown_A	413327737	412465814	0	0
TlulRdataKnown_A	413327737	412465814	0	0
TlulReadOnReadLock_A	413327737	7713	0	0
TlulRerrorKnown_A	413327737	412465814	0	0
TlulRvalidKnown_A	413327737	412465814	0	0
WriteLockPropagation_A	413327737	2892952	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	413327737	29553527	0	0
u_state_regs_A	413327737	412465814	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	3836	0	0
T49	15203	0	0	0
T79	10661	3836	0	0
T108	12003	0	0	0
T161	15806	0	0	0
T162	17244	0	0	0
T163	52732	0	0	0
T164	23527	0	0	0
T165	13311	0	0	0
T166	218092	0	0	0
T167	10165	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	87635636	0	0
T1	10220	5188	0	0
T2	55365	10337	0	0
T3	810642	128071	0	0
T4	24914	687	0	0
T5	670883	89616	0	0
T8	15226	6928	0	0
T9	14820	3437	0	0
T10	77406	2557	0	0
T11	163838	16414	0	0
T12	10063	3942	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	87635636	0	0
T1	10220	5188	0	0
T2	55365	10337	0	0
T3	810642	128071	0	0
T4	24914	687	0	0
T5	670883	89616	0	0
T8	15226	6928	0	0
T9	14820	3437	0	0
T10	77406	2557	0	0
T11	163838	16414	0	0
T12	10063	3942	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	46	0	0
T28	88604	0	0	0
T32	11719	0	0	0
T53	9929	0	0	0
T70	14796	0	0	0
T93	0	1	0	0
T97	47555	0	0	0
T150	0	1	0	0
T153	123468	1	0	0
T155	10347	0	0	0
T158	8797	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T177	10251	0	0	0
T190	38714	0	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	178434735	0	0
T3	810642	124286	0	0
T4	24914	0	0	0
T5	670883	104179	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	14263	0	0
T11	163838	2683	0	0
T12	10063	0	0	0
T16	0	3140	0	0
T28	0	5517	0	0
T38	0	45679	0	0
T76	0	33560	0	0
T97	0	5921	0	0
T103	14453	0	0	0
T104	122681	0	0	0
T153	0	3183	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	7713	0	0
T2	55365	7	0	0
T3	810642	33	0	0
T4	24914	0	0	0
T5	670883	26	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	6	0	0
T11	163838	1	0	0
T12	10063	0	0	0
T16	0	1	0	0
T38	0	13	0	0
T103	14453	0	0	0
T104	0	8	0	0
T153	0	25	0	0
T190	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	2892952	0	0
T3	810642	25571	0	0
T4	24914	0	0	0
T5	670883	0	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	10039	0	0
T11	163838	26694	0	0
T12	10063	0	0	0
T38	0	42631	0	0
T96	0	1916	0	0
T98	0	19910	0	0
T101	0	4857	0	0
T102	0	8827	0	0
T103	14453	0	0	0
T104	122681	0	0	0
T105	0	7434	0	0
T112	0	8328	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	29553527	0	0
T3	810642	435204	0	0
T4	24914	0	0	0
T5	670883	92312	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	60022	0	0
T11	163838	152012	0	0
T12	10063	0	0	0
T16	0	35613	0	0
T28	0	74736	0	0
T38	0	204331	0	0
T97	0	19365	0	0
T98	0	90408	0	0
T103	14453	0	0	0
T104	122681	0	0	0
T153	0	2437	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T119,T25

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T2,T11,T153

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T79,T143,T157
1	Covered	T79,T143,T157

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T8
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T12,T103,T107
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T1,T155,T93
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T10,T5
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T182,T202,T203
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T79,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T10,T5
CheckFailError	317	Covered	T79,T143,T157
FsmStateError	289	Covered	T2,T3,T8
MacroEccCorrError	221	Covered	T2,T11,T153
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T204,T15
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T10,T38
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T79,T143,T157
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T8
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T2,T153,T35
MacroEccCorrError->NoError	235	Covered	T11,T153,T76
NoError->AccessError	256	Covered	T3,T10,T5
NoError->CheckFailError	317	Covered	T79,T143,T157
NoError->FsmStateError	289	Covered	T2,T3,T8
NoError->MacroEccCorrError	221	Covered	T2,T11,T153

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T35,T119,T25
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T155,T205
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T96,T111
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T10,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T2,T11,T153
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T182,T202,T203
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T79,T143,T157
1	0	Covered	T79,T143,T157
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	413327737	412465814	0	0
DigestKnown_A	413327737	412465814	0	0
DigestOffsetMustBeRepresentable_A	1143	1143	0	0
EccErrorState_A	413327737	9912	0	0
ErrorKnown_A	413327737	412465814	0	0
FsmStateKnown_A	413327737	412465814	0	0
InitDoneKnown_A	413327737	412465814	0	0
InitReadLocksPartition_A	413327737	87813101	0	0
InitWriteLocksPartition_A	413327737	87813101	0	0
OffsetMustBeBlockAligned_A	1143	1143	0	0
OtpAddrKnown_A	413327737	412465814	0	0
OtpCmdKnown_A	413327737	412465814	0	0
OtpErrorState_A	413327737	31	0	0
OtpReqKnown_A	413327737	412465814	0	0
OtpSizeKnown_A	413327737	412465814	0	0
OtpWdataKnown_A	413327737	412465814	0	0
ReadLockPropagation_A	413327737	184717832	0	0
SizeMustBeBlockAligned_A	1143	1143	0	0
TlulGntKnown_A	413327737	412465814	0	0
TlulRdataKnown_A	413327737	412465814	0	0
TlulReadOnReadLock_A	413327737	7520	0	0
TlulRerrorKnown_A	413327737	412465814	0	0
TlulRvalidKnown_A	413327737	412465814	0	0
WriteLockPropagation_A	413327737	851636	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	413327737	13957232	0	0
u_state_regs_A	413327737	412465814	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	9912	0	0
T49	15203	0	0	0
T79	10661	3836	0	0
T108	12003	0	0	0
T143	0	3279	0	0
T157	0	2797	0	0
T161	15806	0	0	0
T162	17244	0	0	0
T163	52732	0	0	0
T164	23527	0	0	0
T165	13311	0	0	0
T166	218092	0	0	0
T167	10165	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	87813101	0	0
T1	10220	5212	0	0
T2	55365	10609	0	0
T3	810642	129584	0	0
T4	24914	789	0	0
T5	670883	89990	0	0
T8	15226	6962	0	0
T9	14820	3488	0	0
T10	77406	2676	0	0
T11	163838	16686	0	0
T12	10063	3959	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	87813101	0	0
T1	10220	5212	0	0
T2	55365	10609	0	0
T3	810642	129584	0	0
T4	24914	789	0	0
T5	670883	89990	0	0
T8	15226	6962	0	0
T9	14820	3488	0	0
T10	77406	2676	0	0
T11	163838	16686	0	0
T12	10063	3959	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	31	0	0
T1	10220	1	0	0
T2	55365	0	0	0
T3	810642	0	0	0
T4	24914	0	0	0
T5	670883	0	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	0	0	0
T11	163838	0	0	0
T12	10063	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T182	0	2	0	0
T202	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	184717832	0	0
T3	810642	120165	0	0
T4	24914	0	0	0
T5	670883	94619	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	9289	0	0
T11	163838	0	0	0
T12	10063	0	0	0
T16	0	3027	0	0
T28	0	15936	0	0
T38	0	43222	0	0
T76	0	23230	0	0
T97	0	5381	0	0
T98	0	45433	0	0
T103	14453	0	0	0
T104	122681	0	0	0
T153	0	3181	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	7520	0	0
T2	55365	6	0	0
T3	810642	32	0	0
T4	24914	0	0	0
T5	670883	14	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	1	0	0
T11	163838	3	0	0
T12	10063	0	0	0
T28	0	1	0	0
T38	0	10	0	0
T97	0	1	0	0
T103	14453	0	0	0
T104	0	8	0	0
T153	0	15	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	851636	0	0
T16	41682	2658	0	0
T28	88604	15393	0	0
T32	11719	0	0	0
T53	9929	0	0	0
T76	149117	0	0	0
T78	0	32080	0	0
T84	15900	0	0	0
T97	47555	0	0	0
T99	0	2192	0	0
T100	0	4322	0	0
T111	0	3859	0	0
T116	0	34324	0	0
T125	0	7963	0	0
T158	8797	0	0	0
T177	10251	0	0	0
T190	38714	0	0	0
T210	0	5798	0	0
T211	0	30087	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	13957232	0	0
T1	10220	2602	0	0
T2	55365	11089	0	0
T3	810642	13621	0	0
T4	24914	0	0	0
T5	670883	92261	0	0
T8	15226	0	0	0
T9	14820	0	0	0
T10	77406	0	0	0
T11	163838	0	0	0
T12	10063	0	0	0
T16	0	35528	0	0
T28	0	74481	0	0
T38	0	204110	0	0
T104	0	43097	0	0
T132	0	2886	0	0
T155	0	2161	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413327737	412465814	0	0
T1	10220	10041	0	0
T2	55365	54097	0	0
T3	810642	803312	0	0
T4	24914	24433	0	0
T5	670883	669093	0	0
T8	15226	14944	0	0
T9	14820	14574	0	0
T10	77406	76884	0	0
T11	163838	162550	0	0
T12	10063	9822	0	0