Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

23999467

1

T1

1740

T2

651

T3

1699

full_word

7888566

1

T1

1423

T2

212

T3

155

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31887743	1			T1	3163		T2	863		T3	1854
auto[TlIntgErrCmd]	90	1			T274	9		T275	4		T276	4
auto[TlIntgErrData]	98	1			T274	6		T275	2		T276	2
auto[TlIntgErrBoth]	102	1			T274	5		T275	4		T276	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9499339

1

T1

2647

T2

597

T3

1756

auto[1]

22388694

1

T1

516

T2

266

T3

98

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6030315	1			T1	1473		T2	505		T3	1636
auto[TlIntgErrNone]	partial	auto[1]	17968879	1			T1	267		T2	146		T3	63
auto[TlIntgErrNone]	full_word	auto[0]	3468899	1			T1	1174		T2	92		T3	120
auto[TlIntgErrNone]	full_word	auto[1]	4419650	1			T1	249		T2	120		T3	35
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T274	4		T275	2		T276	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T274	5		T275	2		T276	3
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T389	1		T390	1		-	-
auto[TlIntgErrData]	partial	auto[0]	44	1			T274	1		T276	1		T281	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T274	3		T275	2		T276	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T274	1		T391	1		T392	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T274	1		T393	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T274	2		T275	2		T276	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T274	2		T275	2		T276	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T394	1		T395	1		T396	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T274	1		T279	2		T397	1