Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.23	94.16	96.15	97.24		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	461202723	7578479	0	0
check_regwen_rd_A	461202723	2050	0	0
check_timeout_rd_A	461202723	1688	0	0
check_trigger_regwen_rd_A	461202723	2215	0	0
consistency_check_period_rd_A	461202723	2056	0	0
creator_sw_cfg_read_lock_rd_A	461202723	1695	0	0
direct_access_address_rd_A	461202723	1058	0	0
direct_access_wdata_0_rd_A	461202723	614	0	0
direct_access_wdata_1_rd_A	461202723	826	0	0
integrity_check_period_rd_A	461202723	2180	0	0
intr_enable_rd_A	461202723	2848	0	0
owner_sw_cfg_read_lock_rd_A	461202723	1484	0	0
rot_creator_auth_codesign_read_lock_rd_A	461202723	1536	0	0
rot_creator_auth_state_read_lock_rd_A	461202723	1483	0	0
vendor_test_read_lock_rd_A	461202723	1463	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	7578479	0	0
T6	196555	32776	0	0
T13	0	261941	0	0
T14	0	13750	0	0
T15	5034	0	0	0
T17	0	45525	0	0
T27	0	57201	0	0
T34	0	118074	0	0
T42	15577	0	0	0
T70	14212	0	0	0
T141	0	237959	0	0
T142	0	152340	0	0
T161	136394	0	0	0
T165	15332	0	0	0
T173	9991	0	0	0
T174	10986	0	0	0
T175	15509	0	0	0
T184	0	20732	0	0
T188	0	153836	0	0
T254	73426	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	2050	0	0
T18	0	29	0	0
T222	12743	0	0	0
T265	641541	91	0	0
T266	261029	59	0	0
T300	0	20	0	0
T357	0	34	0	0
T358	0	27	0	0
T359	0	55	0	0
T360	0	44	0	0
T361	0	53	0	0
T362	0	79	0	0
T363	31084	0	0	0
T364	58279	0	0	0
T365	14524	0	0	0
T366	302076	0	0	0
T367	10054	0	0	0
T368	14090	0	0	0
T369	28739	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	1688	0	0
T18	0	79	0	0
T222	12743	0	0	0
T265	641541	94	0	0
T266	261029	68	0	0
T300	0	17	0	0
T357	0	36	0	0
T358	0	92	0	0
T359	0	61	0	0
T360	0	90	0	0
T361	0	35	0	0
T362	0	97	0	0
T363	31084	0	0	0
T364	58279	0	0	0
T365	14524	0	0	0
T366	302076	0	0	0
T367	10054	0	0	0
T368	14090	0	0	0
T369	28739	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	2215	0	0
T18	0	98	0	0
T222	12743	0	0	0
T265	641541	67	0	0
T266	261029	40	0	0
T300	0	43	0	0
T357	0	59	0	0
T358	0	48	0	0
T359	0	76	0	0
T360	0	35	0	0
T361	0	41	0	0
T362	0	95	0	0
T363	31084	0	0	0
T364	58279	0	0	0
T365	14524	0	0	0
T366	302076	0	0	0
T367	10054	0	0	0
T368	14090	0	0	0
T369	28739	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	2056	0	0
T18	0	87	0	0
T222	12743	0	0	0
T265	641541	102	0	0
T266	261029	57	0	0
T300	0	7	0	0
T357	0	35	0	0
T358	0	34	0	0
T359	0	71	0	0
T360	0	85	0	0
T361	0	54	0	0
T362	0	78	0	0
T363	31084	0	0	0
T364	58279	0	0	0
T365	14524	0	0	0
T366	302076	0	0	0
T367	10054	0	0	0
T368	14090	0	0	0
T369	28739	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	1695	0	0
T18	0	95	0	0
T222	12743	0	0	0
T265	641541	79	0	0
T266	261029	83	0	0
T300	0	29	0	0
T357	0	51	0	0
T358	0	52	0	0
T359	0	92	0	0
T360	0	85	0	0
T361	0	30	0	0
T362	0	100	0	0
T363	31084	0	0	0
T364	58279	0	0	0
T365	14524	0	0	0
T366	302076	0	0	0
T367	10054	0	0	0
T368	14090	0	0	0
T369	28739	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	1058	0	0
T18	0	84	0	0
T222	12743	0	0	0
T265	641541	126	0	0
T266	261029	60	0	0
T300	0	7	0	0
T357	0	46	0	0
T358	0	96	0	0
T359	0	64	0	0
T360	0	68	0	0
T361	0	30	0	0
T362	0	99	0	0
T363	31084	0	0	0
T364	58279	0	0	0
T365	14524	0	0	0
T366	302076	0	0	0
T367	10054	0	0	0
T368	14090	0	0	0
T369	28739	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	614	0	0
T18	0	58	0	0
T222	12743	0	0	0
T265	641541	54	0	0
T266	261029	28	0	0
T300	0	4	0	0
T357	0	13	0	0
T358	0	57	0	0
T359	0	27	0	0
T360	0	51	0	0
T361	0	10	0	0
T362	0	77	0	0
T363	31084	0	0	0
T364	58279	0	0	0
T365	14524	0	0	0
T366	302076	0	0	0
T367	10054	0	0	0
T368	14090	0	0	0
T369	28739	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	826	0	0
T18	0	79	0	0
T222	12743	0	0	0
T265	641541	91	0	0
T266	261029	41	0	0
T300	0	29	0	0
T357	0	34	0	0
T358	0	38	0	0
T359	0	45	0	0
T360	0	62	0	0
T361	0	42	0	0
T362	0	55	0	0
T363	31084	0	0	0
T364	58279	0	0	0
T365	14524	0	0	0
T366	302076	0	0	0
T367	10054	0	0	0
T368	14090	0	0	0
T369	28739	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	2180	0	0
T18	0	84	0	0
T222	12743	0	0	0
T265	641541	102	0	0
T266	261029	53	0	0
T300	0	22	0	0
T357	0	42	0	0
T358	0	37	0	0
T359	0	65	0	0
T360	0	78	0	0
T361	0	25	0	0
T362	0	73	0	0
T363	31084	0	0	0
T364	58279	0	0	0
T365	14524	0	0	0
T366	302076	0	0	0
T367	10054	0	0	0
T368	14090	0	0	0
T369	28739	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	2848	0	0
T17	223552	0	0	0
T59	171965	6	0	0
T60	152942	0	0	0
T76	11862	0	0	0
T100	61205	0	0	0
T169	45060	0	0	0
T201	13221	0	0	0
T235	0	29	0	0
T236	30735	0	0	0
T249	0	10	0	0
T265	0	104	0	0
T266	0	73	0	0
T357	0	105	0	0
T358	0	63	0	0
T359	0	40	0	0
T360	0	63	0	0
T370	0	15	0	0
T371	99341	0	0	0
T372	17290	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	1484	0	0
T18	0	89	0	0
T222	12743	0	0	0
T265	641541	102	0	0
T266	261029	55	0	0
T300	0	41	0	0
T357	0	24	0	0
T358	0	43	0	0
T359	0	66	0	0
T360	0	67	0	0
T361	0	28	0	0
T362	0	110	0	0
T363	31084	0	0	0
T364	58279	0	0	0
T365	14524	0	0	0
T366	302076	0	0	0
T367	10054	0	0	0
T368	14090	0	0	0
T369	28739	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	1536	0	0
T18	0	71	0	0
T222	12743	0	0	0
T265	641541	71	0	0
T266	261029	40	0	0
T300	0	23	0	0
T357	0	54	0	0
T358	0	37	0	0
T359	0	87	0	0
T360	0	76	0	0
T361	0	38	0	0
T362	0	102	0	0
T363	31084	0	0	0
T364	58279	0	0	0
T365	14524	0	0	0
T366	302076	0	0	0
T367	10054	0	0	0
T368	14090	0	0	0
T369	28739	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	1483	0	0
T18	0	58	0	0
T222	12743	0	0	0
T265	641541	98	0	0
T266	261029	77	0	0
T300	0	30	0	0
T357	0	74	0	0
T358	0	20	0	0
T359	0	44	0	0
T360	0	79	0	0
T361	0	47	0	0
T362	0	103	0	0
T363	31084	0	0	0
T364	58279	0	0	0
T365	14524	0	0	0
T366	302076	0	0	0
T367	10054	0	0	0
T368	14090	0	0	0
T369	28739	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461202723	1463	0	0
T18	0	63	0	0
T222	12743	0	0	0
T265	641541	80	0	0
T266	261029	41	0	0
T300	0	24	0	0
T357	0	44	0	0
T358	0	42	0	0
T359	0	85	0	0
T360	0	100	0	0
T361	0	59	0	0
T362	0	98	0	0
T363	31084	0	0	0
T364	58279	0	0	0
T365	14524	0	0	0
T366	302076	0	0	0
T367	10054	0	0	0
T368	14090	0	0	0
T369	28739	0	0	0