Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6882886	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6641853

1

T1

354

T2

131

T3

252

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8016244	1			T1	676		T2	304		T3	742
values[0x0]	2111220	1			T1	62		T2	68		T3	155
values[0x1]	3397275	1			T1	67		T2	77		T3	174

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4508439	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9016300

1

T1

450

T2

225

T3

466

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51358	1			T1	4		T3	4		T4	5
valid_sources[0x01]	114949	1			T1	1		T4	5		T7	109
valid_sources[0x02]	58282	1			T1	5		T4	5		T7	122
valid_sources[0x03]	50866	1			T1	3		T3	2		T4	1
valid_sources[0x04]	49330	1			T1	5		T3	9		T4	3
valid_sources[0x05]	45167	1			T1	1		T4	5		T7	132
valid_sources[0x06]	140701	1			T1	2		T3	2		T4	5
valid_sources[0x07]	46864	1			T1	3		T3	19		T4	5
valid_sources[0x08]	46959	1			T1	6		T3	11		T4	3
valid_sources[0x09]	44849	1			T1	2		T3	7		T4	5
valid_sources[0x0a]	48230	1			T1	3		T3	1		T4	1
valid_sources[0x0b]	114318	1			T1	3		T3	8		T4	7
valid_sources[0x0c]	46164	1			T1	1		T4	3		T7	207
valid_sources[0x0d]	55380	1			T1	4		T3	3		T4	7
valid_sources[0x0e]	48042	1			T1	2		T3	12		T4	7
valid_sources[0x0f]	49902	1			T1	4		T3	12		T4	6
valid_sources[0x10]	49235	1			T1	1		T4	2		T7	185
valid_sources[0x11]	70173	1			T1	2		T3	9		T4	5
valid_sources[0x12]	46208	1			T1	1		T3	3		T4	6
valid_sources[0x13]	49983	1			T1	3		T3	1		T4	2
valid_sources[0x14]	47780	1			T1	1		T4	7		T7	247
valid_sources[0x15]	71791	1			T3	6		T4	1		T11	20
valid_sources[0x16]	50606	1			T1	1		T3	2		T4	5
valid_sources[0x17]	47480	1			T1	3		T3	15		T4	7
valid_sources[0x18]	55679	1			T1	3		T4	4		T11	14
valid_sources[0x19]	47411	1			T1	6		T3	7		T4	4
valid_sources[0x1a]	51159	1			T1	4		T3	2		T4	4
valid_sources[0x1b]	56740	1			T1	9		T3	1		T4	4
valid_sources[0x1c]	50058	1			T3	9		T4	5		T11	35
valid_sources[0x1d]	44577	1			T1	6		T4	2		T11	15
valid_sources[0x1e]	52467	1			T1	3		T4	6		T7	184
valid_sources[0x1f]	53127	1			T1	3		T3	9		T4	2
valid_sources[0x20]	55323	1			T1	6		T4	3		T11	12
valid_sources[0x21]	47484	1			T1	7		T3	19		T4	3
valid_sources[0x22]	46468	1			T1	3		T4	5		T7	328
valid_sources[0x23]	49232	1			T1	6		T3	22		T4	7
valid_sources[0x24]	48331	1			T1	5		T3	2		T4	4
valid_sources[0x25]	47221	1			T3	9		T4	6		T7	115
valid_sources[0x26]	45891	1			T1	3		T3	4		T11	2
valid_sources[0x27]	46994	1			T1	5		T4	2		T7	51
valid_sources[0x28]	49679	1			T1	3		T4	7		T7	48
valid_sources[0x29]	61692	1			T1	1		T3	15		T4	7
valid_sources[0x2a]	47109	1			T1	4		T4	7		T7	111
valid_sources[0x2b]	57081	1			T1	1		T3	13		T4	2
valid_sources[0x2c]	51053	1			T1	5		T3	5		T4	4
valid_sources[0x2d]	44675	1			T1	3		T3	9		T7	111
valid_sources[0x2e]	64478	1			T1	3		T3	3		T4	7
valid_sources[0x2f]	47774	1			T1	2		T3	1		T4	2
valid_sources[0x30]	48956	1			T1	3		T4	2		T11	33
valid_sources[0x31]	48865	1			T1	3		T3	4		T4	3
valid_sources[0x32]	50193	1			T1	1		T3	1		T4	2
valid_sources[0x33]	44374	1			T1	3		T4	6		T11	9
valid_sources[0x34]	46150	1			T1	1		T3	7		T4	5
valid_sources[0x35]	61105	1			T1	1		T3	4		T4	8
valid_sources[0x36]	50804	1			T1	1		T4	3		T11	65
valid_sources[0x37]	48995	1			T1	6		T4	3		T11	25
valid_sources[0x38]	49208	1			T1	3		T3	14		T4	3
valid_sources[0x39]	46705	1			T1	2		T3	9		T4	4
valid_sources[0x3a]	45591	1			T1	1		T3	4		T4	4
valid_sources[0x3b]	47434	1			T1	4		T3	6		T4	4
valid_sources[0x3c]	48682	1			T1	2		T3	23		T4	2
valid_sources[0x3d]	47725	1			T1	2		T3	2		T4	6
valid_sources[0x3e]	48047	1			T1	5		T4	2		T11	19
valid_sources[0x3f]	46120	1			T1	2		T4	6		T7	78
valid_sources[0x40]	46725	1			T3	26		T4	6		T7	432
valid_sources[0x41]	50129	1			T1	4		T4	2		T7	381
valid_sources[0x42]	46688	1			T1	3		T4	3		T7	509
valid_sources[0x43]	44317	1			T1	3		T3	3		T4	4
valid_sources[0x44]	44195	1			T4	5		T7	91		T12	13
valid_sources[0x45]	47177	1			T1	5		T3	3		T4	5
valid_sources[0x46]	51192	1			T1	7		T4	1		T11	11
valid_sources[0x47]	56436	1			T1	3		T4	3		T7	62
valid_sources[0x48]	48992	1			T1	4		T4	6		T7	94
valid_sources[0x49]	47159	1			T1	2		T3	13		T4	5
valid_sources[0x4a]	83258	1			T1	2		T4	3		T7	107
valid_sources[0x4b]	47658	1			T1	1		T3	14		T4	3
valid_sources[0x4c]	55526	1			T1	3		T3	5		T4	7
valid_sources[0x4d]	48248	1			T1	1		T4	3		T11	14
valid_sources[0x4e]	54820	1			T1	3		T4	3		T11	10
valid_sources[0x4f]	49827	1			T1	1		T3	9		T4	5
valid_sources[0x50]	48272	1			T1	1		T4	2		T7	221
valid_sources[0x51]	44774	1			T1	2		T3	17		T4	1
valid_sources[0x52]	51184	1			T1	5		T3	15		T4	1
valid_sources[0x53]	59828	1			T1	5		T3	1		T4	6
valid_sources[0x54]	58521	1			T1	5		T4	4		T11	15
valid_sources[0x55]	154577	1			T1	3		T3	6		T4	6
valid_sources[0x56]	47412	1			T1	6		T4	3		T7	32
valid_sources[0x57]	53622	1			T1	2		T3	3		T4	6
valid_sources[0x58]	49076	1			T1	1		T3	15		T4	3
valid_sources[0x59]	50261	1			T1	3		T3	1		T4	5
valid_sources[0x5a]	48481	1			T1	2		T3	1		T4	3
valid_sources[0x5b]	62522	1			T1	7		T3	5		T4	3
valid_sources[0x5c]	50584	1			T1	2		T3	4		T4	1
valid_sources[0x5d]	47927	1			T1	4		T3	8		T4	6
valid_sources[0x5e]	52413	1			T1	2		T3	3		T4	8
valid_sources[0x5f]	55489	1			T1	1		T3	16		T4	2
valid_sources[0x60]	46678	1			T1	5		T3	6		T4	2
valid_sources[0x61]	46962	1			T1	3		T3	1		T4	2
valid_sources[0x62]	46128	1			T1	5		T4	2		T11	3
valid_sources[0x63]	48909	1			T4	5		T11	18		T7	52
valid_sources[0x64]	65776	1			T3	4		T4	5		T11	17
valid_sources[0x65]	56385	1			T3	1		T4	7		T7	43
valid_sources[0x66]	45089	1			T1	1		T3	14		T4	3
valid_sources[0x67]	119255	1			T1	6		T3	3		T4	3
valid_sources[0x68]	52127	1			T1	3		T3	3		T4	7
valid_sources[0x69]	46895	1			T1	8		T4	4		T7	682
valid_sources[0x6a]	61210	1			T1	8		T3	5		T4	5
valid_sources[0x6b]	55723	1			T1	4		T7	169		T12	9
valid_sources[0x6c]	48506	1			T1	1		T3	1		T4	2
valid_sources[0x6d]	54210	1			T1	6		T3	4		T4	6
valid_sources[0x6e]	50597	1			T1	1		T4	7		T7	27
valid_sources[0x6f]	47436	1			T3	2		T4	3		T7	235
valid_sources[0x70]	48233	1			T1	1		T3	18		T4	4
valid_sources[0x71]	50693	1			T1	5		T4	4		T11	2
valid_sources[0x72]	50560	1			T1	3		T3	13		T4	7
valid_sources[0x73]	53248	1			T1	2		T3	8		T4	6
valid_sources[0x74]	59994	1			T1	5		T4	5		T7	143
valid_sources[0x75]	50534	1			T1	1		T3	5		T4	5
valid_sources[0x76]	44938	1			T1	4		T3	8		T4	5
valid_sources[0x77]	45599	1			T1	3		T3	2		T4	4
valid_sources[0x78]	47720	1			T1	5		T3	1		T4	1
valid_sources[0x79]	46577	1			T1	3		T3	7		T4	4
valid_sources[0x7a]	45705	1			T1	3		T4	3		T7	48
valid_sources[0x7b]	49633	1			T1	3		T7	162		T12	2
valid_sources[0x7c]	44463	1			T1	2		T3	2		T4	3
valid_sources[0x7d]	48341	1			T1	5		T3	10		T4	3
valid_sources[0x7e]	51637	1			T4	6		T7	41		T12	5
valid_sources[0x7f]	51585	1			T1	5		T3	8		T4	4
valid_sources[0x80]	50544	1			T1	3		T3	1		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3252513

1

T1

301

T2

57

T3

125

values[0x0]

all_enables

biggest_size

1733064

1

T1

31

T2

40

T3

87

values[0x1]

all_enables

biggest_size

1656276

1

T1

22

T2

34

T3

40

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	222082	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7958294

1

T1

40

T11

20

T6

140

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2038714	1			T1	20		T11	10		T6	70
values[0x0]	2983058	1			T1	13		T11	6		T6	35
values[0x1]	3158604	1			T1	7		T11	4		T6	35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	81081	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8099295

1

T1

40

T11

20

T6

140

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32578	1			T6	1		T7	228		T9	465
valid_sources[0x01]	31937	1			T1	2		T7	252		T9	536
valid_sources[0x02]	33733	1			T7	231		T9	498		T30	1
valid_sources[0x03]	30872	1			T6	1		T7	259		T29	1
valid_sources[0x04]	31317	1			T11	1		T7	261		T9	458
valid_sources[0x05]	32123	1			T7	215		T9	501		T14	203
valid_sources[0x06]	31410	1			T11	4		T6	1		T7	258
valid_sources[0x07]	32458	1			T7	217		T9	558		T39	1
valid_sources[0x08]	31837	1			T7	245		T9	505		T114	5
valid_sources[0x09]	31953	1			T7	233		T9	529		T146	3
valid_sources[0x0a]	30817	1			T7	259		T9	494		T146	1
valid_sources[0x0b]	32757	1			T7	217		T9	470		T146	1
valid_sources[0x0c]	32274	1			T6	1		T7	232		T9	521
valid_sources[0x0d]	32605	1			T7	241		T29	4		T9	528
valid_sources[0x0e]	31409	1			T6	1		T7	234		T9	496
valid_sources[0x0f]	32264	1			T6	1		T7	257		T29	6
valid_sources[0x10]	33208	1			T11	1		T7	250		T9	492
valid_sources[0x11]	32422	1			T6	2		T7	274		T9	503
valid_sources[0x12]	31052	1			T7	248		T9	559		T14	508
valid_sources[0x13]	31006	1			T6	2		T7	295		T9	451
valid_sources[0x14]	32814	1			T7	240		T9	514		T113	1
valid_sources[0x15]	34062	1			T6	1		T7	222		T9	511
valid_sources[0x16]	31250	1			T7	234		T9	491		T146	2
valid_sources[0x17]	31927	1			T6	1		T7	269		T9	520
valid_sources[0x18]	32766	1			T6	1		T7	251		T9	457
valid_sources[0x19]	32032	1			T7	213		T9	490		T146	3
valid_sources[0x1a]	32700	1			T7	232		T9	497		T39	1
valid_sources[0x1b]	29615	1			T6	3		T7	260		T29	4
valid_sources[0x1c]	31595	1			T7	242		T9	551		T39	1
valid_sources[0x1d]	31652	1			T7	251		T9	549		T146	1
valid_sources[0x1e]	32734	1			T7	220		T9	516		T14	273
valid_sources[0x1f]	30501	1			T1	2		T7	260		T9	509
valid_sources[0x20]	33000	1			T7	263		T29	6		T9	533
valid_sources[0x21]	32790	1			T1	4		T6	1		T7	263
valid_sources[0x22]	32590	1			T7	219		T9	502		T14	545
valid_sources[0x23]	34266	1			T7	242		T9	532		T146	1
valid_sources[0x24]	31902	1			T6	1		T7	229		T106	120
valid_sources[0x25]	31515	1			T7	258		T9	503		T113	1
valid_sources[0x26]	31352	1			T6	1		T7	236		T105	2
valid_sources[0x27]	32016	1			T7	209		T9	479		T146	3
valid_sources[0x28]	32438	1			T6	3		T7	208		T9	545
valid_sources[0x29]	31621	1			T11	1		T7	267		T9	489
valid_sources[0x2a]	32416	1			T7	260		T9	526		T146	2
valid_sources[0x2b]	31894	1			T7	249		T8	1		T9	500
valid_sources[0x2c]	31323	1			T6	1		T7	262		T29	2
valid_sources[0x2d]	32313	1			T7	233		T9	546		T14	290
valid_sources[0x2e]	31693	1			T11	1		T7	239		T9	484
valid_sources[0x2f]	31706	1			T7	236		T9	479		T146	1
valid_sources[0x30]	31136	1			T6	2		T7	218		T29	1
valid_sources[0x31]	32912	1			T6	1		T7	261		T9	489
valid_sources[0x32]	32212	1			T11	2		T7	245		T29	2
valid_sources[0x33]	31962	1			T7	228		T29	4		T9	518
valid_sources[0x34]	30954	1			T6	1		T7	254		T29	4
valid_sources[0x35]	32279	1			T6	2		T7	248		T9	488
valid_sources[0x36]	32263	1			T7	233		T9	513		T39	2
valid_sources[0x37]	32223	1			T7	222		T9	476		T146	2
valid_sources[0x38]	30647	1			T7	268		T105	7		T29	10
valid_sources[0x39]	31323	1			T7	253		T9	461		T30	3
valid_sources[0x3a]	32453	1			T11	1		T7	234		T9	499
valid_sources[0x3b]	31634	1			T6	1		T7	263		T9	461
valid_sources[0x3c]	32233	1			T6	2		T7	225		T8	6
valid_sources[0x3d]	31234	1			T1	2		T7	243		T9	488
valid_sources[0x3e]	31837	1			T6	1		T7	228		T29	1
valid_sources[0x3f]	32549	1			T7	263		T9	569		T30	2
valid_sources[0x40]	32957	1			T6	1		T7	257		T9	493
valid_sources[0x41]	32197	1			T6	1		T7	236		T29	10
valid_sources[0x42]	32913	1			T7	258		T8	10		T9	532
valid_sources[0x43]	30807	1			T6	1		T7	235		T9	485
valid_sources[0x44]	32590	1			T6	1		T7	268		T9	538
valid_sources[0x45]	31797	1			T7	278		T9	494		T146	1
valid_sources[0x46]	32086	1			T1	2		T7	266		T9	577
valid_sources[0x47]	32577	1			T7	262		T29	4		T9	512
valid_sources[0x48]	30938	1			T7	223		T9	475		T146	1
valid_sources[0x49]	31531	1			T11	1		T7	261		T9	510
valid_sources[0x4a]	32023	1			T7	227		T9	510		T30	2
valid_sources[0x4b]	33598	1			T6	1		T7	234		T9	519
valid_sources[0x4c]	31889	1			T7	250		T9	492		T30	1
valid_sources[0x4d]	34437	1			T6	1		T7	258		T9	513
valid_sources[0x4e]	33546	1			T6	1		T7	226		T9	515
valid_sources[0x4f]	32291	1			T1	1		T7	233		T9	480
valid_sources[0x50]	33480	1			T7	246		T9	506		T146	1
valid_sources[0x51]	31943	1			T7	237		T9	515		T146	1
valid_sources[0x52]	31426	1			T6	1		T7	256		T9	501
valid_sources[0x53]	31604	1			T7	293		T29	12		T9	541
valid_sources[0x54]	31686	1			T7	263		T9	445		T30	2
valid_sources[0x55]	33208	1			T7	246		T9	524		T146	1
valid_sources[0x56]	31907	1			T1	1		T7	234		T9	533
valid_sources[0x57]	32127	1			T7	262		T9	487		T10	3
valid_sources[0x58]	32258	1			T7	253		T9	538		T146	1
valid_sources[0x59]	31486	1			T7	234		T9	464		T14	106
valid_sources[0x5a]	34186	1			T6	1		T7	247		T9	518
valid_sources[0x5b]	31851	1			T6	1		T7	224		T9	445
valid_sources[0x5c]	32890	1			T7	202		T9	554		T14	326
valid_sources[0x5d]	31128	1			T6	1		T7	222		T9	528
valid_sources[0x5e]	32085	1			T1	2		T6	3		T7	233
valid_sources[0x5f]	31250	1			T7	249		T9	426		T30	1
valid_sources[0x60]	32539	1			T1	1		T7	256		T9	472
valid_sources[0x61]	32556	1			T1	1		T7	221		T9	507
valid_sources[0x62]	31907	1			T7	222		T8	1		T9	477
valid_sources[0x63]	30100	1			T7	252		T29	2		T9	503
valid_sources[0x64]	32650	1			T7	265		T9	495		T146	1
valid_sources[0x65]	31901	1			T7	231		T9	522		T146	1
valid_sources[0x66]	31968	1			T1	3		T7	216		T9	520
valid_sources[0x67]	30300	1			T6	2		T7	232		T9	502
valid_sources[0x68]	30340	1			T6	1		T7	203		T9	481
valid_sources[0x69]	34244	1			T6	1		T7	233		T9	487
valid_sources[0x6a]	31101	1			T6	1		T7	254		T9	516
valid_sources[0x6b]	30296	1			T7	257		T9	509		T30	2
valid_sources[0x6c]	30876	1			T7	244		T29	3		T9	514
valid_sources[0x6d]	31809	1			T7	234		T9	501		T14	170
valid_sources[0x6e]	31073	1			T1	1		T7	243		T9	504
valid_sources[0x6f]	32424	1			T1	1		T7	237		T9	513
valid_sources[0x70]	32399	1			T6	1		T7	245		T9	492
valid_sources[0x71]	32473	1			T7	250		T9	483		T146	1
valid_sources[0x72]	31905	1			T7	235		T9	519		T14	718
valid_sources[0x73]	31691	1			T6	2		T7	254		T9	480
valid_sources[0x74]	32710	1			T6	1		T7	239		T9	469
valid_sources[0x75]	31835	1			T6	1		T7	248		T9	543
valid_sources[0x76]	32317	1			T6	2		T7	234		T105	6
valid_sources[0x77]	31989	1			T6	2		T7	250		T9	465
valid_sources[0x78]	31177	1			T6	2		T7	238		T9	525
valid_sources[0x79]	32440	1			T7	235		T9	520		T14	523
valid_sources[0x7a]	32962	1			T7	190		T29	2		T9	497
valid_sources[0x7b]	31795	1			T7	237		T9	514		T39	1
valid_sources[0x7c]	31851	1			T6	1		T7	252		T9	500
valid_sources[0x7d]	31261	1			T1	2		T6	1		T7	275
valid_sources[0x7e]	32115	1			T6	1		T7	194		T9	492
valid_sources[0x7f]	29990	1			T7	243		T9	535		T146	1
valid_sources[0x80]	32680	1			T7	254		T9	453		T14	174

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2025056

1

T1

20

T11

10

T6

70

values[0x0]

all_enables

biggest_size

2967742

1

T1

13

T11

6

T6

35

values[0x1]

all_enables

biggest_size

2965496

1

T1

7

T11

4

T6

35