Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

22835720

1

T1

451

T2

318

T3

819

full_word

7608385

1

T1

354

T2

131

T3

252

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30443795	1			T1	805		T2	449		T3	1071
auto[TlIntgErrCmd]	111	1			T269	3		T270	4		T271	8
auto[TlIntgErrData]	106	1			T269	4		T270	8		T271	8
auto[TlIntgErrBoth]	93	1			T269	3		T270	8		T271	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9183898

1

T1

676

T2

304

T3

742

auto[1]

21260207

1

T1

129

T2

145

T3

329

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5813279	1			T1	375		T2	247		T3	617
auto[TlIntgErrNone]	partial	auto[1]	17022147	1			T1	76		T2	71		T3	202
auto[TlIntgErrNone]	full_word	auto[0]	3370483	1			T1	301		T2	57		T3	125
auto[TlIntgErrNone]	full_word	auto[1]	4237886	1			T1	53		T2	74		T3	127
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T269	2		T270	2		T271	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T269	1		T270	2		T271	5
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T345	2		T346	1		T347	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T269	1		T270	4		T271	5
auto[TlIntgErrData]	partial	auto[1]	47	1			T269	2		T270	4		T271	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T269	1		T348	1		T346	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T274	2		T349	1		T350	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T270	3		T271	1		T351	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T269	3		T270	5		T271	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T273	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T346	1		T350	1		-	-