Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.08		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	425739846	7182415	0	0
check_regwen_rd_A	425739846	3165	0	0
check_timeout_rd_A	425739846	2179	0	0
check_trigger_regwen_rd_A	425739846	3118	0	0
consistency_check_period_rd_A	425739846	3264	0	0
creator_sw_cfg_read_lock_rd_A	425739846	2128	0	0
direct_access_address_rd_A	425739846	1519	0	0
direct_access_wdata_0_rd_A	425739846	1027	0	0
direct_access_wdata_1_rd_A	425739846	1103	0	0
integrity_check_period_rd_A	425739846	3291	0	0
intr_enable_rd_A	425739846	4023	0	0
owner_sw_cfg_read_lock_rd_A	425739846	2047	0	0
rot_creator_auth_codesign_read_lock_rd_A	425739846	2291	0	0
rot_creator_auth_state_read_lock_rd_A	425739846	2081	0	0
vendor_test_read_lock_rd_A	425739846	2160	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	7182415	0	0
T7	256852	55885	0	0
T8	41866	0	0	0
T9	424980	116785	0	0
T12	11466	0	0	0
T13	16232	0	0	0
T14	0	86535	0	0
T17	0	103365	0	0
T18	0	140964	0	0
T28	0	79778	0	0
T29	95125	0	0	0
T38	0	63318	0	0
T39	34375	0	0	0
T105	7264	0	0	0
T106	16159	0	0	0
T110	0	10859	0	0
T146	80048	0	0	0
T182	0	135305	0	0
T243	0	28247	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	3165	0	0
T14	432991	64	0	0
T17	0	81	0	0
T19	0	140	0	0
T25	13776	0	0	0
T43	14860	0	0	0
T44	12469	0	0	0
T50	137361	0	0	0
T51	45355	0	0	0
T59	10577	0	0	0
T109	23312	0	0	0
T110	899349	0	0	0
T115	26076	0	0	0
T243	0	51	0	0
T275	0	153	0	0
T297	0	113	0	0
T320	0	53	0	0
T326	0	88	0	0
T327	0	45	0	0
T328	0	22	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	2179	0	0
T14	432991	54	0	0
T17	0	59	0	0
T19	0	241	0	0
T25	13776	0	0	0
T43	14860	0	0	0
T44	12469	0	0	0
T50	137361	0	0	0
T51	45355	0	0	0
T59	10577	0	0	0
T109	23312	0	0	0
T110	899349	0	0	0
T115	26076	0	0	0
T243	0	65	0	0
T275	0	206	0	0
T297	0	47	0	0
T320	0	43	0	0
T326	0	90	0	0
T327	0	45	0	0
T328	0	58	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	3118	0	0
T14	432991	82	0	0
T17	0	59	0	0
T19	0	112	0	0
T25	13776	0	0	0
T43	14860	0	0	0
T44	12469	0	0	0
T50	137361	0	0	0
T51	45355	0	0	0
T59	10577	0	0	0
T109	23312	0	0	0
T110	899349	0	0	0
T115	26076	0	0	0
T243	0	36	0	0
T275	0	159	0	0
T297	0	63	0	0
T320	0	57	0	0
T326	0	100	0	0
T327	0	36	0	0
T328	0	48	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	3264	0	0
T14	432991	86	0	0
T17	0	79	0	0
T19	0	127	0	0
T25	13776	0	0	0
T43	14860	0	0	0
T44	12469	0	0	0
T50	137361	0	0	0
T51	45355	0	0	0
T59	10577	0	0	0
T109	23312	0	0	0
T110	899349	0	0	0
T115	26076	0	0	0
T243	0	39	0	0
T275	0	239	0	0
T297	0	54	0	0
T320	0	56	0	0
T326	0	122	0	0
T327	0	39	0	0
T328	0	37	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	2128	0	0
T14	432991	78	0	0
T17	0	66	0	0
T19	0	147	0	0
T25	13776	0	0	0
T43	14860	0	0	0
T44	12469	0	0	0
T50	137361	0	0	0
T51	45355	0	0	0
T59	10577	0	0	0
T109	23312	0	0	0
T110	899349	0	0	0
T115	26076	0	0	0
T243	0	35	0	0
T275	0	159	0	0
T297	0	92	0	0
T320	0	79	0	0
T326	0	100	0	0
T327	0	52	0	0
T328	0	37	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	1519	0	0
T14	432991	70	0	0
T17	0	94	0	0
T19	0	171	0	0
T25	13776	0	0	0
T43	14860	0	0	0
T44	12469	0	0	0
T50	137361	0	0	0
T51	45355	0	0	0
T59	10577	0	0	0
T109	23312	0	0	0
T110	899349	0	0	0
T115	26076	0	0	0
T243	0	44	0	0
T275	0	150	0	0
T297	0	50	0	0
T320	0	77	0	0
T326	0	106	0	0
T327	0	51	0	0
T328	0	40	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	1027	0	0
T14	432991	27	0	0
T17	0	46	0	0
T19	0	161	0	0
T25	13776	0	0	0
T43	14860	0	0	0
T44	12469	0	0	0
T50	137361	0	0	0
T51	45355	0	0	0
T59	10577	0	0	0
T109	23312	0	0	0
T110	899349	0	0	0
T115	26076	0	0	0
T243	0	12	0	0
T275	0	141	0	0
T297	0	40	0	0
T320	0	17	0	0
T326	0	34	0	0
T327	0	32	0	0
T328	0	9	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	1103	0	0
T14	432991	38	0	0
T17	0	68	0	0
T19	0	102	0	0
T25	13776	0	0	0
T43	14860	0	0	0
T44	12469	0	0	0
T50	137361	0	0	0
T51	45355	0	0	0
T59	10577	0	0	0
T109	23312	0	0	0
T110	899349	0	0	0
T115	26076	0	0	0
T243	0	39	0	0
T275	0	158	0	0
T297	0	61	0	0
T320	0	38	0	0
T326	0	63	0	0
T327	0	4	0	0
T328	0	28	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	3291	0	0
T14	432991	44	0	0
T17	0	54	0	0
T19	0	154	0	0
T25	13776	0	0	0
T43	14860	0	0	0
T44	12469	0	0	0
T50	137361	0	0	0
T51	45355	0	0	0
T59	10577	0	0	0
T109	23312	0	0	0
T110	899349	0	0	0
T115	26076	0	0	0
T243	0	63	0	0
T275	0	184	0	0
T297	0	62	0	0
T320	0	62	0	0
T326	0	84	0	0
T327	0	38	0	0
T328	0	22	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	4023	0	0
T14	432991	61	0	0
T17	0	88	0	0
T19	0	206	0	0
T25	13776	0	0	0
T43	14860	0	0	0
T44	12469	0	0	0
T50	137361	0	0	0
T51	45355	0	0	0
T59	10577	0	0	0
T109	23312	0	0	0
T110	899349	0	0	0
T115	26076	0	0	0
T235	0	13	0	0
T243	0	51	0	0
T247	0	9	0	0
T326	0	98	0	0
T327	0	58	0	0
T328	0	30	0	0
T329	0	40	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	2047	0	0
T14	432991	58	0	0
T17	0	75	0	0
T19	0	141	0	0
T25	13776	0	0	0
T43	14860	0	0	0
T44	12469	0	0	0
T50	137361	0	0	0
T51	45355	0	0	0
T59	10577	0	0	0
T109	23312	0	0	0
T110	899349	0	0	0
T115	26076	0	0	0
T243	0	42	0	0
T275	0	162	0	0
T297	0	65	0	0
T320	0	74	0	0
T326	0	80	0	0
T327	0	74	0	0
T328	0	49	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	2291	0	0
T14	432991	80	0	0
T17	0	71	0	0
T19	0	167	0	0
T25	13776	0	0	0
T43	14860	0	0	0
T44	12469	0	0	0
T50	137361	0	0	0
T51	45355	0	0	0
T59	10577	0	0	0
T109	23312	0	0	0
T110	899349	0	0	0
T115	26076	0	0	0
T243	0	34	0	0
T275	0	222	0	0
T297	0	75	0	0
T320	0	68	0	0
T326	0	99	0	0
T327	0	32	0	0
T328	0	28	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	2081	0	0
T14	432991	53	0	0
T17	0	83	0	0
T19	0	147	0	0
T25	13776	0	0	0
T43	14860	0	0	0
T44	12469	0	0	0
T50	137361	0	0	0
T51	45355	0	0	0
T59	10577	0	0	0
T109	23312	0	0	0
T110	899349	0	0	0
T115	26076	0	0	0
T243	0	54	0	0
T275	0	181	0	0
T297	0	49	0	0
T320	0	92	0	0
T326	0	57	0	0
T327	0	34	0	0
T328	0	49	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425739846	2160	0	0
T14	432991	54	0	0
T17	0	97	0	0
T19	0	178	0	0
T25	13776	0	0	0
T43	14860	0	0	0
T44	12469	0	0	0
T50	137361	0	0	0
T51	45355	0	0	0
T59	10577	0	0	0
T109	23312	0	0	0
T110	899349	0	0	0
T115	26076	0	0	0
T243	0	34	0	0
T275	0	182	0	0
T297	0	110	0	0
T320	0	72	0	0
T326	0	52	0	0
T327	0	46	0	0
T328	0	31	0	0