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Module Instance : tb.dut.u_otp_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.29 98.07 97.35 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.29 98.07 97.35 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.20 94.16 96.15 97.08 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instances:
tb.dut.u_otp_arb
Line Coverage for Instance : tb.dut.u_otp_arb
Line No.TotalCoveredPercent
TOTAL20720398.07
CONT_ASSIGN6211100.00
CONT_ASSIGN11211100.00
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CONT_ASSIGN112100.00
CONT_ASSIGN11811100.00
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CONT_ASSIGN11811100.00
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CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
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CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
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CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
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CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
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CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
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CONT_ASSIGN13811100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14811100.00
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CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
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CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14800
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
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CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15000
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
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CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
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CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15100
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN155100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN156100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
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CONT_ASSIGN16011100.00
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CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16000
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
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CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
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CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
112 13 14
118 14 14
122 13 14
126 14 14
128 14 14
138 2 2
148 14 14(1 unreachable)
150 14 14(1 unreachable)
151 14 14(1 unreachable)
155 14 15
156 14 15
160 14 14(1 unreachable)
161 15 15
163 11 11(4 unreachable)
164 15 15
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_otp_arb
TotalCoveredPercent
Conditions52951597.35
Logical52951597.35
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
118-15596.81
155-16498.69

Branch Coverage for Instance : tb.dut.u_otp_arb
Line No.TotalCoveredPercent
Branches 88 88 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 1 1 100.00
TERNARY 156 1 1 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T11,T6,T7


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T11,T6,T7


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T11,T6,T7


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T11,T6,T7


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 422770771 421898307 0 0
CheckNGreaterZero_A 1145 1145 0 0
GntImpliesReady_A 422770771 1555504 0 0
GntImpliesValid_A 422770771 1555504 0 0
GrantKnown_A 422770771 421898307 0 0
IdxKnown_A 422770771 421898307 0 0
IndexIsCorrect_A 422770771 1555504 0 0
LockArbDecision_A 422770771 6898634 0 0
NoReadyValidNoGrant_A 422770771 8679326 0 0
ReadyAndValidImplyGrant_A 422770771 1555504 0 0
ReqAndReadyImplyGrant_A 422770771 1555504 0 0
ReqImpliesValid_A 422770771 8455643 0 0
ReqStaysHighUntilGranted0_M 422770771 6898634 0 0
RoundRobin_A 422770771 0 0 1145
ValidKnown_A 422770771 421898307 0 0
gen_data_port_assertion.DataFlow_A 422770771 1555504 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 421898307 0 0
T1 12576 12290 0 0
T2 13420 13166 0 0
T3 15031 14826 0 0
T4 10627 10446 0 0
T5 13105 12864 0 0
T6 102238 101289 0 0
T7 256852 256842 0 0
T11 13053 12746 0 0
T12 11466 11243 0 0
T13 16232 16171 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1145 1145 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 1555504 0 0
T1 12576 179 0 0
T2 13420 160 0 0
T3 15031 249 0 0
T4 10627 148 0 0
T5 13105 212 0 0
T6 102238 1294 0 0
T7 256852 5254 0 0
T11 13053 292 0 0
T12 11466 247 0 0
T13 16232 55 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 1555504 0 0
T1 12576 179 0 0
T2 13420 160 0 0
T3 15031 249 0 0
T4 10627 148 0 0
T5 13105 212 0 0
T6 102238 1294 0 0
T7 256852 5254 0 0
T11 13053 292 0 0
T12 11466 247 0 0
T13 16232 55 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 421898307 0 0
T1 12576 12290 0 0
T2 13420 13166 0 0
T3 15031 14826 0 0
T4 10627 10446 0 0
T5 13105 12864 0 0
T6 102238 101289 0 0
T7 256852 256842 0 0
T11 13053 12746 0 0
T12 11466 11243 0 0
T13 16232 16171 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 421898307 0 0
T1 12576 12290 0 0
T2 13420 13166 0 0
T3 15031 14826 0 0
T4 10627 10446 0 0
T5 13105 12864 0 0
T6 102238 101289 0 0
T7 256852 256842 0 0
T11 13053 12746 0 0
T12 11466 11243 0 0
T13 16232 16171 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 1555504 0 0
T1 12576 179 0 0
T2 13420 160 0 0
T3 15031 249 0 0
T4 10627 148 0 0
T5 13105 212 0 0
T6 102238 1294 0 0
T7 256852 5254 0 0
T11 13053 292 0 0
T12 11466 247 0 0
T13 16232 55 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 6898634 0 0
T1 12576 1872 0 0
T2 13420 1268 0 0
T3 15031 1248 0 0
T4 10627 724 0 0
T5 13105 1708 0 0
T6 102238 8513 0 0
T7 256852 6666 0 0
T11 13053 2352 0 0
T12 11466 1248 0 0
T13 16232 624 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 8679326 0 0
T1 12576 883 0 0
T2 13420 1089 0 0
T3 15031 2161 0 0
T4 10627 1137 0 0
T5 13105 1183 0 0
T6 102238 7453 0 0
T7 256852 29875 0 0
T11 13053 1600 0 0
T12 11466 2016 0 0
T13 16232 242 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 1555504 0 0
T1 12576 179 0 0
T2 13420 160 0 0
T3 15031 249 0 0
T4 10627 148 0 0
T5 13105 212 0 0
T6 102238 1294 0 0
T7 256852 5254 0 0
T11 13053 292 0 0
T12 11466 247 0 0
T13 16232 55 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 1555504 0 0
T1 12576 179 0 0
T2 13420 160 0 0
T3 15031 249 0 0
T4 10627 148 0 0
T5 13105 212 0 0
T6 102238 1294 0 0
T7 256852 5254 0 0
T11 13053 292 0 0
T12 11466 247 0 0
T13 16232 55 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 8455643 0 0
T1 12576 2051 0 0
T2 13420 1430 0 0
T3 15031 1497 0 0
T4 10627 874 0 0
T5 13105 1922 0 0
T6 102238 9808 0 0
T7 256852 11923 0 0
T11 13053 2645 0 0
T12 11466 1495 0 0
T13 16232 679 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 6898634 0 0
T1 12576 1872 0 0
T2 13420 1268 0 0
T3 15031 1248 0 0
T4 10627 724 0 0
T5 13105 1708 0 0
T6 102238 8513 0 0
T7 256852 6666 0 0
T11 13053 2352 0 0
T12 11466 1248 0 0
T13 16232 624 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 0 0 1145

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 421898307 0 0
T1 12576 12290 0 0
T2 13420 13166 0 0
T3 15031 14826 0 0
T4 10627 10446 0 0
T5 13105 12864 0 0
T6 102238 101289 0 0
T7 256852 256842 0 0
T11 13053 12746 0 0
T12 11466 11243 0 0
T13 16232 16171 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422770771 1555504 0 0
T1 12576 179 0 0
T2 13420 160 0 0
T3 15031 249 0 0
T4 10627 148 0 0
T5 13105 212 0 0
T6 102238 1294 0 0
T7 256852 5254 0 0
T11 13053 292 0 0
T12 11466 247 0 0
T13 16232 55 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%