Line Coverage for Instance : tb.dut.u_otp_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 207 | 203 | 98.07 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 0 | 0 | |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 0 | 0 | |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 0 | 0 | |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
1 |
1 |
112 |
13 |
14 |
118 |
14 |
14 |
122 |
13 |
14 |
126 |
14 |
14 |
128 |
14 |
14 |
138 |
2 |
2 |
148 |
14 |
14(1 unreachable) |
150 |
14 |
14(1 unreachable) |
151 |
14 |
14(1 unreachable) |
155 |
14 |
15 |
156 |
14 |
15 |
160 |
14 |
14(1 unreachable) |
161 |
15 |
15 |
163 |
11 |
11(4 unreachable) |
164 |
15 |
15 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_otp_arb
| Total | Covered | Percent |
Conditions | 529 | 515 | 97.35 |
Logical | 529 | 515 | 97.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Branch Coverage for Instance : tb.dut.u_otp_arb
| Line No. | Total | Covered | Percent |
Branches |
|
88 |
88 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
1 |
1 |
100.00 |
TERNARY |
156 |
1 |
1 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T11,T6,T7 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T11,T6,T7 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T11,T6,T7 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T11,T6,T7 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Unreachable |
|
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Unreachable |
|
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_otp_arb
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
421898307 |
0 |
0 |
T1 |
12576 |
12290 |
0 |
0 |
T2 |
13420 |
13166 |
0 |
0 |
T3 |
15031 |
14826 |
0 |
0 |
T4 |
10627 |
10446 |
0 |
0 |
T5 |
13105 |
12864 |
0 |
0 |
T6 |
102238 |
101289 |
0 |
0 |
T7 |
256852 |
256842 |
0 |
0 |
T11 |
13053 |
12746 |
0 |
0 |
T12 |
11466 |
11243 |
0 |
0 |
T13 |
16232 |
16171 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1145 |
1145 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
1555504 |
0 |
0 |
T1 |
12576 |
179 |
0 |
0 |
T2 |
13420 |
160 |
0 |
0 |
T3 |
15031 |
249 |
0 |
0 |
T4 |
10627 |
148 |
0 |
0 |
T5 |
13105 |
212 |
0 |
0 |
T6 |
102238 |
1294 |
0 |
0 |
T7 |
256852 |
5254 |
0 |
0 |
T11 |
13053 |
292 |
0 |
0 |
T12 |
11466 |
247 |
0 |
0 |
T13 |
16232 |
55 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
1555504 |
0 |
0 |
T1 |
12576 |
179 |
0 |
0 |
T2 |
13420 |
160 |
0 |
0 |
T3 |
15031 |
249 |
0 |
0 |
T4 |
10627 |
148 |
0 |
0 |
T5 |
13105 |
212 |
0 |
0 |
T6 |
102238 |
1294 |
0 |
0 |
T7 |
256852 |
5254 |
0 |
0 |
T11 |
13053 |
292 |
0 |
0 |
T12 |
11466 |
247 |
0 |
0 |
T13 |
16232 |
55 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
421898307 |
0 |
0 |
T1 |
12576 |
12290 |
0 |
0 |
T2 |
13420 |
13166 |
0 |
0 |
T3 |
15031 |
14826 |
0 |
0 |
T4 |
10627 |
10446 |
0 |
0 |
T5 |
13105 |
12864 |
0 |
0 |
T6 |
102238 |
101289 |
0 |
0 |
T7 |
256852 |
256842 |
0 |
0 |
T11 |
13053 |
12746 |
0 |
0 |
T12 |
11466 |
11243 |
0 |
0 |
T13 |
16232 |
16171 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
421898307 |
0 |
0 |
T1 |
12576 |
12290 |
0 |
0 |
T2 |
13420 |
13166 |
0 |
0 |
T3 |
15031 |
14826 |
0 |
0 |
T4 |
10627 |
10446 |
0 |
0 |
T5 |
13105 |
12864 |
0 |
0 |
T6 |
102238 |
101289 |
0 |
0 |
T7 |
256852 |
256842 |
0 |
0 |
T11 |
13053 |
12746 |
0 |
0 |
T12 |
11466 |
11243 |
0 |
0 |
T13 |
16232 |
16171 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
1555504 |
0 |
0 |
T1 |
12576 |
179 |
0 |
0 |
T2 |
13420 |
160 |
0 |
0 |
T3 |
15031 |
249 |
0 |
0 |
T4 |
10627 |
148 |
0 |
0 |
T5 |
13105 |
212 |
0 |
0 |
T6 |
102238 |
1294 |
0 |
0 |
T7 |
256852 |
5254 |
0 |
0 |
T11 |
13053 |
292 |
0 |
0 |
T12 |
11466 |
247 |
0 |
0 |
T13 |
16232 |
55 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
6898634 |
0 |
0 |
T1 |
12576 |
1872 |
0 |
0 |
T2 |
13420 |
1268 |
0 |
0 |
T3 |
15031 |
1248 |
0 |
0 |
T4 |
10627 |
724 |
0 |
0 |
T5 |
13105 |
1708 |
0 |
0 |
T6 |
102238 |
8513 |
0 |
0 |
T7 |
256852 |
6666 |
0 |
0 |
T11 |
13053 |
2352 |
0 |
0 |
T12 |
11466 |
1248 |
0 |
0 |
T13 |
16232 |
624 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
8679326 |
0 |
0 |
T1 |
12576 |
883 |
0 |
0 |
T2 |
13420 |
1089 |
0 |
0 |
T3 |
15031 |
2161 |
0 |
0 |
T4 |
10627 |
1137 |
0 |
0 |
T5 |
13105 |
1183 |
0 |
0 |
T6 |
102238 |
7453 |
0 |
0 |
T7 |
256852 |
29875 |
0 |
0 |
T11 |
13053 |
1600 |
0 |
0 |
T12 |
11466 |
2016 |
0 |
0 |
T13 |
16232 |
242 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
1555504 |
0 |
0 |
T1 |
12576 |
179 |
0 |
0 |
T2 |
13420 |
160 |
0 |
0 |
T3 |
15031 |
249 |
0 |
0 |
T4 |
10627 |
148 |
0 |
0 |
T5 |
13105 |
212 |
0 |
0 |
T6 |
102238 |
1294 |
0 |
0 |
T7 |
256852 |
5254 |
0 |
0 |
T11 |
13053 |
292 |
0 |
0 |
T12 |
11466 |
247 |
0 |
0 |
T13 |
16232 |
55 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
1555504 |
0 |
0 |
T1 |
12576 |
179 |
0 |
0 |
T2 |
13420 |
160 |
0 |
0 |
T3 |
15031 |
249 |
0 |
0 |
T4 |
10627 |
148 |
0 |
0 |
T5 |
13105 |
212 |
0 |
0 |
T6 |
102238 |
1294 |
0 |
0 |
T7 |
256852 |
5254 |
0 |
0 |
T11 |
13053 |
292 |
0 |
0 |
T12 |
11466 |
247 |
0 |
0 |
T13 |
16232 |
55 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
8455643 |
0 |
0 |
T1 |
12576 |
2051 |
0 |
0 |
T2 |
13420 |
1430 |
0 |
0 |
T3 |
15031 |
1497 |
0 |
0 |
T4 |
10627 |
874 |
0 |
0 |
T5 |
13105 |
1922 |
0 |
0 |
T6 |
102238 |
9808 |
0 |
0 |
T7 |
256852 |
11923 |
0 |
0 |
T11 |
13053 |
2645 |
0 |
0 |
T12 |
11466 |
1495 |
0 |
0 |
T13 |
16232 |
679 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
6898634 |
0 |
0 |
T1 |
12576 |
1872 |
0 |
0 |
T2 |
13420 |
1268 |
0 |
0 |
T3 |
15031 |
1248 |
0 |
0 |
T4 |
10627 |
724 |
0 |
0 |
T5 |
13105 |
1708 |
0 |
0 |
T6 |
102238 |
8513 |
0 |
0 |
T7 |
256852 |
6666 |
0 |
0 |
T11 |
13053 |
2352 |
0 |
0 |
T12 |
11466 |
1248 |
0 |
0 |
T13 |
16232 |
624 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
0 |
0 |
1145 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
421898307 |
0 |
0 |
T1 |
12576 |
12290 |
0 |
0 |
T2 |
13420 |
13166 |
0 |
0 |
T3 |
15031 |
14826 |
0 |
0 |
T4 |
10627 |
10446 |
0 |
0 |
T5 |
13105 |
12864 |
0 |
0 |
T6 |
102238 |
101289 |
0 |
0 |
T7 |
256852 |
256842 |
0 |
0 |
T11 |
13053 |
12746 |
0 |
0 |
T12 |
11466 |
11243 |
0 |
0 |
T13 |
16232 |
16171 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422770771 |
1555504 |
0 |
0 |
T1 |
12576 |
179 |
0 |
0 |
T2 |
13420 |
160 |
0 |
0 |
T3 |
15031 |
249 |
0 |
0 |
T4 |
10627 |
148 |
0 |
0 |
T5 |
13105 |
212 |
0 |
0 |
T6 |
102238 |
1294 |
0 |
0 |
T7 |
256852 |
5254 |
0 |
0 |
T11 |
13053 |
292 |
0 |
0 |
T12 |
11466 |
247 |
0 |
0 |
T13 |
16232 |
55 |
0 |
0 |